4-Bit Magnitude Comparator Project

[John Kimble]

I'm having trouble understanding what these do. Could someone explain it in easy-to-understand terms?

Every website I've come across has the same definition and it's just too hard to understand even with my electronics knowledge.


Thanks.

 

[MikeM]

John Kimble wrote:

I'm having trouble understanding what these do. Could someone explain it in easy-to-understand terms?

Every website I've come across has the same definition and it's just too hard to understand even with my electronics knowledge.


Thanks.

Black box which compares the magnitude of two four-bit binary
numbers, A3,A2,A1,A0 and B3,B2,B1,B0. The range of these
two numbers is 0 to 15 decimal, each.

It usually produces three outputs:
">" is true if A>B,
"=" is true if A=B,
"<" is true if A<B.

It sometimes has three additional inputs, <, =, >, which can
be used to "cascade" multiple comparitors so as to make
possible magnitude comparison of binary numbers wider than
four bits...

MikeM

 

[R. Steve Walz]

John Kimble wrote:

I'm having trouble understanding what these do. Could someone explain it in easy-to-understand terms?

Every website I've come across has the same definition and it's just too hard to understand even with my electronics knowledge.

Thanks.
----------------------------

http://www.semiconductors.philips.com/pip/74HCT85.html
The logic diagram is contained within.

All you need to do to understand it is conceive of a decoder that
activates three outputs labeled "=" "<" and ">" according to whether
one 4-bit nibble input is =, <, or > the other nibble input.

A decoder is just an in-out box that takes a binary number in and
selects a specific output or specific outputs. They are assembled
by using two complementary inverters (in series) each output routed
to a column of lines, each of which represents the proposition of
an input to the chip being "1" or "0". Then inputs to a final bank
of AND gates and then a final OR gate combining them, if need be,
for each output are selectively wired to this column of proposition
lines.

See my site for examples of decoders of a few kinds:

http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS154.gif
(best example of complementary inverter chained inputs, and
vertical column of proposition lines, and N/AND outputs.

Also:
http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS138.gif
http://www.armory.com/~rstevew/Public/Tutor/Boolean/7447logic.gif
(Note that the BCD to 7-seg display contverter is also just a
decoder, a decoder is just a gate-array with a rank of inputs
and a rank of outputs. It can be expressed in Boolean equations.

Decoders can be implemented in EPROM or GALs and PLDs or in discrete
TTL gate chips, or in single MSI packages like the '138, '154, '47,
and in processors, in fact microcode in uC's and uP's is often
implemented with decoders and latching and counting logic.

-Steve
--
-Steve Walz rstevew@armory.com ftp://ftp.armory.com/pub/user/rstevew
Electronics Site!! 1000's of Files and Dirs!! With Schematics Galore!!
http://www.armory.com/~rstevew or http://www.armory.com/~rstevew/Public

 

[petrus bitbyter]

"John Kimble" <JohnKimble@JohnKimble.com> schreef in bericht
news:nCp8c.67239$8G2.25283@fe3.columbus.rr.com...

I'm having trouble understanding what these do. Could someone explain it
in easy-to-understand terms?

Every website I've come across has the same definition and it's just too
hard to understand even with my electronics knowledge.


Thanks.

Having electronics knowledge you should be able to read a datasheet of the
74LS85 or one of its successors. It's all in it. Description, truthtabel and
some application data.

petrus


---
Outgoing mail is certified Virus Free.
Checked by AVG anti-virus system (http://www.grisoft.com).
Version: 6.0.639 / Virus Database: 408 - Release Date: 22-3-2004