VHDL Language

K
How do we declare a signed integer?
Replies
2
Views
394
Kwaj
K
K
How do we declare a signed integer?
Replies
2
Views
408
Kwaj
K
K
Creating a new type for STD_LOGIC_VECTOR
Replies
3
Views
348
Lee
L
K
Creating a new type for STD_LOGIC_VECTOR
Replies
3
Views
407
Lee
L
L
VHDL or Verilog, which one is more porpular in industry?Than
Replies
2
Views
358
Jim Lewis
J
L
VHDL or Verilog, which one is more porpular in industry?Than
Replies
2
Views
448
Jim Lewis
J
S
Generics and state machines
Replies
7
Views
543
Andreas Hinze
A
S
Generics and state machines
Replies
7
Views
458
Andreas Hinze
A
J
process sentence in synthesis
Replies
3
Views
323
Riyaz
R
J
process sentence in synthesis
Replies
3
Views
445
Riyaz
R
C
modelsim cosimulation on different PCs
Replies
2
Views
342
Jim Lewis
J
C
modelsim cosimulation on different PCs
Replies
2
Views
383
Jim Lewis
J
S
Xilinx ISE schematic design
Replies
0
Views
116
Sleep Mode
S
S
Xilinx ISE schematic design
Replies
0
Views
319
Sleep Mode
S
A
Shift operator
Replies
0
Views
103
Andreas
A
A
Shift operator
Replies
0
Views
293
Andreas
A
A
Single byte addressable, multiple byte readout.
Replies
1
Views
331
Jonathan Bromley
J
A
Single byte addressable, multiple byte readout.
Replies
1
Views
434
Jonathan Bromley
J
K
Representing signed numbers in VHDL
Replies
0
Views
116
Kingsley Oteng
K
K
Representing signed numbers in VHDL
Replies
0
Views
303
Kingsley Oteng
K
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