VHDL Language

K
How do we declare a signed integer?
Replies
2
Views
438
Kwaj
K
K
How do we declare a signed integer?
Replies
2
Views
452
Kwaj
K
K
Creating a new type for STD_LOGIC_VECTOR
Replies
3
Views
388
Lee
L
K
Creating a new type for STD_LOGIC_VECTOR
Replies
3
Views
447
Lee
L
L
VHDL or Verilog, which one is more porpular in industry?Than
Replies
2
Views
415
Jim Lewis
J
L
VHDL or Verilog, which one is more porpular in industry?Than
Replies
2
Views
504
Jim Lewis
J
S
Generics and state machines
Replies
7
Views
652
Andreas Hinze
A
S
Generics and state machines
Replies
7
Views
511
Andreas Hinze
A
J
process sentence in synthesis
Replies
3
Views
370
Riyaz
R
J
process sentence in synthesis
Replies
3
Views
493
Riyaz
R
C
modelsim cosimulation on different PCs
Replies
2
Views
388
Jim Lewis
J
C
modelsim cosimulation on different PCs
Replies
2
Views
427
Jim Lewis
J
S
Xilinx ISE schematic design
Replies
0
Views
157
Sleep Mode
S
S
Xilinx ISE schematic design
Replies
0
Views
357
Sleep Mode
S
A
Shift operator
Replies
0
Views
142
Andreas
A
A
Shift operator
Replies
0
Views
331
Andreas
A
A
Single byte addressable, multiple byte readout.
Replies
1
Views
370
Jonathan Bromley
J
A
Single byte addressable, multiple byte readout.
Replies
1
Views
491
Jonathan Bromley
J
K
Representing signed numbers in VHDL
Replies
0
Views
153
Kingsley Oteng
K
K
Representing signed numbers in VHDL
Replies
0
Views
343
Kingsley Oteng
K
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