VHDL Language

C
Xilinx ISE : type real
Replies
3
Views
392
David Bishop
D
S
FSM with more than 1 input at each state
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0
Views
174
swiss student
S
S
Process Statements in VHDL
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0
Views
173
samsky electronique
S
?
dlx to three stages
Replies
0
Views
156
-
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B
Hierarchies not the best for video pipelines
Replies
1
Views
290
Mike Treseler
M
?
Loop in procedure not complete
Replies
2
Views
352
john Doef
J
A
Driving signals from a procedure
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2
Views
435
-
?
G
Problem with Clock signals generated by combinational logic
Replies
8
Views
546
Andy Peters
A
M
Warning:Xst:382 - Register A is equivalent to B
Replies
1
Views
317
Andy Peters
A
D
Passing a signal from slow to fast clock
Replies
2
Views
390
Neo
N
D
State machine transition on internal signals - is it legal?
Replies
5
Views
354
Divyang M
D
?
Tristate-Master-Slave testbench description
Replies
4
Views
337
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?
?
NCSIM simulator
Replies
0
Views
172
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G
Business & Spirituality
Replies
0
Views
136
Gar
G
A
wait for signal change
Replies
1
Views
367
Andy Peters
A
J
clockdivider with enable
Replies
3
Views
314
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?
A
Why do VHDL gate level models simulate slower than verilog
Replies
0
Views
177
abilash
A
J
SDRAM AND MICROBLAZE PART 2
Replies
0
Views
181
jluisky
J
N
about hdl testbench
Replies
2
Views
412
Andy Peters
A
B
Advanced Synthesis Techniques
Replies
4
Views
402
Ben Twijnstra
B
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