VHDL Language

P
can we use two foreign attribute in single module?
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0
Views
125
priya
P
R
MAPLD 2005 Postings On-line
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1
Views
142
Bill McCulley
B
?
VHDL for problem
Replies
3
Views
443
Mike Treseler
M
U
modelsim
Replies
3
Views
353
canadianJaouk
C
P
How to run Modelsim for VHDL without using GUI..
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11
Views
837
priya
P
A
How do you change the Modelsim Cursor Resolution (not simula
Replies
0
Views
145
Andrew FPGA
A
P
A 64-bit version of conv_std_logic_vector?
Replies
1
Views
347
Ralf Hildebrandt
R
B
Adding Libraries to Xilinx/ModelSim
Replies
2
Views
295
NOSPAM, Eric
N
G
firmware version
Replies
3
Views
367
Jim Lewis
J
H
numeric_std vias std_logic_unsigned
Replies
3
Views
388
Jim Lewis
J
C
VHDL 2002 differences with 1993?
Replies
2
Views
529
john Doef
J
V
VHDL 2005, VHDL93 and FPHDL
Replies
2
Views
332
Jim Lewis
J
?
Problem with Behav Sim vs Post Place & Route Sim
Replies
2
Views
261
Mike Treseler
M
J
Intialization
Replies
0
Views
115
john
J
B
Board Level Bidirectional Connections
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0
Views
118
Brad Smallridge
B
B
Modelsim Slice error using numeric_std
Replies
5
Views
330
Beanut
B
?
Ripple Clock for a counter
Replies
7
Views
413
jens
J
W
How to pass a global data type to an entity?
Replies
3
Views
327
Weng Tianxiang
W
?
Test vector generation for ethernet frame using VHDL
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1
Views
305
Mike Treseler
M
N
Passing file name to procedure.
Replies
3
Views
335
Mike Treseler
M
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