VHDL Language

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Synthesizeable shared variable?
Replies
1
Views
325
Mike Treseler
M
O
vhdl textio and escape sequences
Replies
1
Views
533
Mike Treseler
M
O
unconstrained args for procedures
Replies
2
Views
348
Andy Peters
A
A
how to convert an integer to std_logic_vector using vhdl
Replies
4
Views
591
Andy Peters
A
?
Best way to generate a sine wave?
Replies
1
Views
349
Jim Lewis
J
O
function args on procedures
Replies
1
Views
344
john Doef
J
M
testbench techniques
Replies
8
Views
695
mindenpilot
M
D
Simple for you experienced folks
Replies
7
Views
445
Duane Clark
D
A
interfacing vhdl to a verilog file
Replies
0
Views
180
ashwin
A
G
Component gt_swift_bw_1 is not bound
Replies
9
Views
350
Giox
G
O
mod and div with XST
Replies
1
Views
387
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?
K
6-bit hex
Replies
1
Views
337
Jaakko Varteva
J
A
To all FFT guru's (2048 point FFT on Virtex 2 pro)
Replies
3
Views
413
Jaakko Varteva
J
A
Assertion file update problem in ModeSim (via Tcl script)
Replies
5
Views
420
Alex
A
T
Modelsim and configuration statements
Replies
6
Views
403
Thomas Reinemann
T
K
tool for drawing timing diagrams
Replies
6
Views
376
Rolf Eike Beer
R
K
Transport and inertial delay , resolution fns
Replies
3
Views
326
Charles Bailey
C
S
VME VHDL bench
Replies
7
Views
845
smu
S
K
enum_encoding
Replies
2
Views
380
Mike Treseler
M
C
jtag/ATPG and read-only registers
Replies
0
Views
177
Calvin
C
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