Verilog Language

C
Strange behavior when simulating with IO path delay
Replies
0
Views
535
cy
C
A
UART Implementation
Replies
2
Views
886
Rudolf Usselmann
R
N
Older versions of AMBA related documentation?
Replies
0
Views
552
Nikos Kostis
N
W
A synthesis question about "high-fanout nets"
Replies
3
Views
4K
walter
W
M
memory
Replies
3
Views
940
Jon
J
M
question about reg and wire types
Replies
3
Views
904
Ajeetha Kumari
A
A
Discrepancy in CLB Usage Report
Replies
0
Views
700
Anand P Paralkar
A
A
explicit time units and timescale restore in verilog
Replies
3
Views
2K
Anatoly Gelman
A
M
Clock singals
Replies
1
Views
863
Uwe Bonnes
U
A
Fully defined case statement?
Replies
3
Views
955
Allen Sun
A
J
Need some models and tests coded soon
Replies
0
Views
524
J F
J
H
combinational divider
Replies
1
Views
984
B. Joshua Rosen
B
N
Verilog Assertion Problem
Replies
1
Views
846
Srinivasan Venkataramanan
S
R
Program Announcement and Registration Open: 6th MAPLD Int'l
Replies
0
Views
555
Richard B. Katz
R
A
Linting tool for verilog
Replies
1
Views
954
Srinivasan Venkataramanan
S
S
audio video application graphs
Replies
0
Views
725
srini
S
V
LABVIEW V7.0 [2 CDs], SABER DESIGNER V2003.6 - SYNOPSYS - ne
Replies
0
Views
575
vvcd2@ath.forthnet.gr
V
U
cmsg cancel <c2c1cca7-4ed0-4eff-8d1c-75330c5a5008@w40g2000yq
Replies
0
Views
1
last_post_username
L
U
How to write a 16bit comparator in verilog? The resource and
Replies
0
Views
1
last_post_username
L
U
want to enjoy yourself
Replies
0
Views
3
last_post_username
L
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