Verilog Language

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Verilog FAQ version 10.03 released
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HDL books for sale
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350
HDL Book Seller
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How to implement gated clock and/or gated partial circuit in
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4
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882
Ian Poole
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PLI Tracing in NC-Verilog or VCS?
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1
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685
Mayank Bhatia
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Job openings
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374
Stellar
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Bit Error Rate ..Implementation...
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358
Debashish
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Low-cost ASIC tools
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2
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753
Jerry
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Synchronous Binary counter question.
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12
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1K
Bob Perlman
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Verilog Book
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3
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703
Sandhya
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define vs parameter
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3
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749
KimH.K.
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output = clock
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2
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685
Sajan
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Linting
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0
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407
Himal
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Home-made SSI chips
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336
JJ
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dummy projects in VHDL/Verilog
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1
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643
Jim Wu
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Leonardo synthesis tool
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2
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688
Jim Wu
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SRAM vs Cache
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1
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696
KimH.K.
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Mealy & Moore
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2
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910
Sajan
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quick estimates of power and area for typical VLSI circuits
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3
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744
Uncle Noah
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SystemVerilog: "logic" or "ulogic?"
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1
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772
Uncle Noah
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Seeking Free ASIC Design Kit.
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4
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781
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