Verilog Language

G
Why syntax error when accessing bits of an array word?
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3
Views
656
Gammaburst
G
M
pass parameter to `include
Replies
4
Views
826
Chris
C
A
DDFS technique problem in generating a few clocks
Replies
6
Views
830
Jonathan Bromley
J
B
how to detect inout contention
Replies
2
Views
771
Hung Truong
H
P
Verilog Header files
Replies
1
Views
2K
Steven Sharp
S
M
Verilog simulation library creation with Synopsys DC
Replies
0
Views
464
Milos Becvar
M
D
vcs simulation for memory
Replies
4
Views
899
Srinivasan Venkataramanan
S
I
Final Call for Papers
Replies
0
Views
457
INFO
I
M
Modeling hardware in Matlab/Simulink (delay, etc.)?
Replies
1
Views
824
Tom Hawkins
T
S
Need help with simple PLL simualtion model
Replies
0
Views
342
s.mokhtar
S
S
Is it possible to define a preprocessor macro in Xilinx ISE
Replies
3
Views
2K
Gammaburst
G
P
PCI Express Bus models and Testbenches
Replies
0
Views
673
Paul Richardson
P
S
Will write/verify Verilog for food.
Replies
0
Views
333
Seong Kang
S
J
huh?? compare problem with vector length??
Replies
3
Views
726
ABW
A
R
Zero width concatenation.
Replies
2
Views
1K
ABW
A
G
How to identify verilog compiler at compile-time?
Replies
7
Views
1K
Allan Herriman
A
V
Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk e
Replies
0
Views
321
vladimir
V
V
Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk e
Replies
0
Views
339
vladimir
V
V
Cool test bench generator for testing some devices which des
Replies
1
Views
890
vladimir
V
S
Formal Verification Survey
Replies
0
Views
436
Sebastian Jaeger
S
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