Verilog Language

M
Verilog Instance Arrays and Synopsys DC?
Replies
3
Views
968
Steven Sharp
S
N
Xilinx Webpack 6.2 and Verilog `define ?
Replies
1
Views
556
David Jones
D
J
Value of variables
Replies
6
Views
705
Andy Peters
A
D
netlist gen error
Replies
1
Views
634
Andy Peters
A
P
Syn. Warning .
Replies
5
Views
632
Andy Peters
A
S
GPL Cver now supports Cygwin
Replies
0
Views
294
Steve Meyer
S
P
Syn. Warning .
Replies
2
Views
689
Andy Peters
A
J
A question on simulating concurrent processes
Replies
6
Views
819
Jie Zhang
J
C
How to define reg ports?
Replies
9
Views
807
Chris Carlen
C
E
Free Parser for Verilog netlists
Replies
0
Views
292
Egon Valentini
E
G
Need Help
Replies
1
Views
631
Mihail Petrov
M
M
blocking and non-blocking ?
Replies
1
Views
639
Jonathan Bromley
J
R
Mixed signal verification using verilog and spice ?
Replies
5
Views
730
jools
J
M
Exponent
Replies
1
Views
633
bj Porcella
B
P
detecting if instance is toplevel
Replies
1
Views
567
Steven Sharp
S
V
spectre model files for use in verilog ams
Replies
0
Views
301
Vineet
V
S
array of module instances
Replies
3
Views
637
sridhar
S
D
Leading Zero count
Replies
11
Views
3K
bj Porcella
B
M
Physical Design Books
Replies
0
Views
274
Marco Lazar
M
A
Sized genvar
Replies
9
Views
2K
Steven Sharp
S
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