Verilog Language

S
d
Replies
0
Views
531
sdf
S
P
Using modelsim for regression
Replies
4
Views
694
Larry Doolittle
L
P
Using modelsim for regression
Replies
4
Views
1K
Larry Doolittle
L
M
High Performance Register File
Replies
3
Views
620
john jakson
J
M
High Performance Register File
Replies
3
Views
677
john jakson
J
C
Comment on my code style
Replies
3
Views
707
Chris Carlen
C
C
Comment on my code style
Replies
3
Views
803
Chris Carlen
C
?
Power estimation for Synopsys Designware IP
Replies
0
Views
259
-
?
?
Power estimation for Synopsys Designware IP
Replies
0
Views
472
-
?
D
To infer or not to infer
Replies
2
Views
583
DW
D
D
To infer or not to infer
Replies
2
Views
671
DW
D
V
sdf_annotate error message
Replies
1
Views
732
ka
K
V
sdf_annotate error message
Replies
1
Views
2K
ka
K
K
Verilog based power estimation tools
Replies
0
Views
274
KaRtiK
K
K
Verilog based power estimation tools
Replies
0
Views
488
KaRtiK
K
A
ASIC RTL and FPGA RTL
Replies
1
Views
613
Alexander Gnusin
A
S
race condition
Replies
3
Views
632
Larry Doolittle
L
S
race condition
Replies
3
Views
709
Larry Doolittle
L
?
stochastic
Replies
0
Views
287
-
?
?
stochastic
Replies
0
Views
468
-
?
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