Verilog Language

?
One big state machine or lots of little ones
Replies
4
Views
556
Robert Finch
R
?
individual DEFINE file in DC
Replies
2
Views
575
-
?
?
CROM
Replies
6
Views
746
Jonathan Bromley
J
H
HELP PLEASE ( verilog and VPI )
Replies
0
Views
154
Henry
H
A
Implicit event_expression list
Replies
7
Views
1K
-
?
J
Overheads of 4-port over 2-port SRAM
Replies
0
Views
180
John T. Goodman
J
?
Please help me with this odd selector design:
Replies
8
Views
719
Gordon Old
G
?
Electronic Design Processes 2005: Call For Papers
Replies
0
Views
124
-
?
M
ncvhdl problem
Replies
2
Views
693
-
?
?
¤Ń¤ôłň¤Ń´I­bAŽy¤KŚĘ¤ŘłćŚěŠĐśĄ¤ŔŻ˛............
Replies
0
Views
245
-
?
J
verilog XL manuals
Replies
2
Views
626
John McBride
J
R
passing arrays to modules
Replies
1
Views
578
John McBride
J
?
History of HDL
Replies
5
Views
542
Oil4war
O
H
vpi_put_value does not assign value to a vpiPartSelect
Replies
0
Views
169
Henry
H
S
Array Assignement in System Verilog
Replies
1
Views
369
Swapnajit Mittra
S
H
Another newbie question
Replies
5
Views
787
Howler
H
?
Tool to report just the list of undeclared signals :
Replies
2
Views
326
Swapnajit Mittra
S
R
Behavior of Arithmetic Right Shift For Verilog 2001
Replies
4
Views
949
glen herrmannsfeldt
G
B
FPGA Engineer Job Posting
Replies
0
Views
189
Brannon King
B
P
Continous assign statement in clock: is it safe?
Replies
0
Views
119
Paul Uiterlinden
P
You must log in or register to post here.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top