Verilog Language

N
Design Compiler and Whiteboxlinux?
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0
Views
239
newuser
N
J
Different ifdef configurations in multiple instantiation
Replies
6
Views
664
Joe
J
D
Variable bit shift
Replies
3
Views
608
John_H
J
D
widthof()
Replies
3
Views
563
Steven Sharp
S
R
Blocking Always with Sensitivity List
Replies
1
Views
350
Steven Sharp
S
L
How to write the modular code?
Replies
3
Views
446
Tom Hawkins
T
H
PKS 5.0/Ambit (Verilog) global define?
Replies
0
Views
180
hmmmm
H
K
SDF Error: IOPATH annotation
Replies
0
Views
416
Kumar
K
?
comp.unix.cray,comp.windows.garnet,comp.os.ms-windows.progra
Replies
0
Views
183
.
?
D
problems with `include and other related stuff
Replies
1
Views
393
DW
D
A
Mentor Precision Synthesis complaint!
Replies
2
Views
502
Andy Peters
A
J
Analog designer needs help: flattening a gate-level verilog
Replies
1
Views
722
rob
R
D
opop
Replies
0
Views
185
Doch
D
R
Glitches and Jitters
Replies
1
Views
699
Blackie Beard
B
S
Power estimation
Replies
4
Views
623
Glen Herrmannsfeldt
G
H
Looking for top Verilog, VHDL reference texts?
Replies
0
Views
181
HDL Book Seller
H
D
Ling Adder
Replies
0
Views
189
David
D
J
Bangalore, India -- VLSI/ASIC/CAD Tech Lead, Parasitic Extra
Replies
1
Views
518
me tew!
M
S
Quick question, may I instantiate a module in a function?
Replies
1
Views
453
Student
S
S
How can I printout the *path* of the instance
Replies
1
Views
471
Jim Wu
J
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