Verilog Language

S
Need Help: trisate problem
Replies
4
Views
418
Steve Pope
S
D
simulator reset, not hardware reset
Replies
7
Views
511
gtwrek@yahoo.com
G
?
implementing a lookup table
Replies
4
Views
418
John_H
J
I
parallel case
Replies
1
Views
487
johnp
J
S
Verilog Simulators
Replies
10
Views
752
ngsayjoe@gmail.com
N
?
Strange execution order
Replies
1
Views
359
Stephen Williams
S
P
how to generate a random time sequency clock signal?
Replies
4
Views
451
Mahurshi Akilla
M
D
How to clarify algorithm of hardware(HDL)?
Replies
2
Views
402
Keith
K
?
synopsys parallel case
Replies
0
Views
164
-
?
C
Is this a race?
Replies
12
Views
494
Chris F Clark
C
J
Verilog Model for a Remote 8-bit I/O Expander
Replies
1
Views
390
Michael
M
?
Simulation Efficiency, continous or procedural ?
Replies
2
Views
367
ngsayjoe@gmail.com
N
D
Makefile question-dynamic source file list creation
Replies
0
Views
170
divsorbit
D
?
pci-express engineer
Replies
0
Views
196
-
?
S
How to interpret results of Synplify Pro
Replies
2
Views
381
Julien Lochen
J
J
Re: testbenches in Verilog for I2C ctrl
Replies
0
Views
172
Julien Lochen
J
J
Re: testbenches in Verilog for I2C ctrl
Replies
0
Views
176
Julien Lochen
J
J
Re: testbenches in Verilog for I2C ctrl
Replies
0
Views
164
Julien Lochen
J
B
can someone please explain on how to go about the following
Replies
5
Views
473
Rob
R
U
How to code a bus of open collector outputs
Replies
4
Views
416
John Penton
J
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