Verilog Language

K
how i declare array for input port
Replies
6
Views
436
Jeremy Ralph
J
?
Read a reg value from the outer module without declaring por
Replies
3
Views
351
-
?
P
icarus/cver and OpenRISC/or1k (orp_soc) from open core
Replies
3
Views
651
Stephen Williams
S
?
urgent: timescale and read_saif
Replies
5
Views
482
Michael
M
A
Pointer in Verilog
Replies
2
Views
702
Jeremy Ralph
J
G
ADD WINGS TO YOUR RESUME !!!!
Replies
0
Views
165
Gopi
G
?
Modeling a serial port in Verilog.
Replies
10
Views
477
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?
D
How can I deal with the output signal in testbech?
Replies
4
Views
377
Ajeetha
A
C
Strange behavior of Mux grammar in Verilog
Replies
4
Views
538
Candida Ferreira
C
F
I need your help. (xor with d-ff)
Replies
3
Views
493
Michael
M
?
how to descripe partly bus connection between two module
Replies
0
Views
122
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?
A
Pointer in Verilog
Replies
1
Views
413
Ron
R
D
Verification by Non-HDL(C++/Java)??
Replies
4
Views
358
mmintz@gmail.com
M
P
Arbiter for the wishbone bus
Replies
0
Views
168
Pooja
P
?
computer bus technology discuss community
Replies
0
Views
161
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?
S
Synplify - Not satisfactory results with re-timing
Replies
0
Views
167
srini
S
H
Error in Synplify Pro Synthesis
Replies
2
Views
512
hnjm
H
?
Do you need delta cycles
Replies
3
Views
418
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?
A
Need a comprehensive Verification Textbook
Replies
3
Views
501
anand
A
F
Modelsim simulation results in tabular format
Replies
5
Views
451
naren
N
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