Verilog Language

N
SDRAM interface through FPGA. How do I ensure no mis-command
Replies
1
Views
366
Edmond Coté
E
3
Behavioral Model Logic Error , BCD to Excess3 converter
Replies
4
Views
457
dbwalker0min@gmail.com
D
G
Being refused for an evaluation license of Questa
Replies
7
Views
2K
Edmond Coté
E
?
XST warnings
Replies
0
Views
156
-
?
N
For SDRAM, is it ok to give it faster refresh rate than data
Replies
4
Views
455
gabor
G
L
3-dimensional memory is not working in VERILOG-XL plzzzzzzz
Replies
3
Views
412
linuxczar
L
L
how to access 4,8-bit words from memory at the same time (32
Replies
2
Views
377
Mike Lewis
M
G
Synthesis of reg with initial value
Replies
1
Views
353
gabor
G
L
3-dimensional memory is not working in VERILOG-XL plzzzzzzz
Replies
0
Views
134
linuxczar
L
B
Verilog operator
Replies
1
Views
443
johnp
J
J
Available: Detailed RISC CPU IP Core Design Documentation
Replies
0
Views
138
John Gulbrandsen
J
A
JTAG Tap Master (was: TI Tap Controller std8980)
Replies
0
Views
144
Amal Khailtash
A
M
register file
Replies
1
Views
449
romi
R
L
Code error
Replies
1
Views
410
gabor
G
R
Testbench environments
Replies
0
Views
136
rsk
R
C
website for VLSI chip designer http://www.vlsichipdesign.com
Replies
0
Views
97
chipdesignart
C
M
3 bit message detector
Replies
2
Views
424
Alex
A
V
gate level simulation problem
Replies
5
Views
686
Ajeetha (www.noveldv.com)
A
V
inferring a dual port memory
Replies
7
Views
539
Verictor
V
R
query
Replies
0
Views
131
ram
R
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