Verilog Language

C
Toggle & line coverage using VCS
Replies
0
Views
165
CS student
C
X
Xilinx Webpack 9.1i.03 Verilog synthesis bug?
Replies
0
Views
136
Xilinx user
X
?
interfacing the keyboard with fpga
Replies
3
Views
465
hmsmith
H
M
setting text aliases to signal values in modelsim waveforms
Replies
2
Views
351
Jonathan Bromley
J
J
fast arbiters (was Re: How to design an abitration cicuit...
Replies
4
Views
468
Quang Anh
Q
E
Declare before use, or vice-versa?
Replies
4
Views
411
Stephen Williams
S
A
waveform
Replies
1
Views
395
dbwalker0min@gmail.com
D
E
'begin_keywords/`end_keywords?
Replies
9
Views
634
Chris F Clark
C
M
Parameterised width assignments
Replies
6
Views
437
Jonathan Bromley
J
M
Specify delays from outside of the cell
Replies
4
Views
354
mk
M
V
help in design
Replies
1
Views
414
Jonathan Bromley
J
V
Custom Software Development
Replies
0
Views
100
VB
V
N
Synthesizing ROM
Replies
3
Views
483
nezhate
N
D
32 bit multiplication
Replies
3
Views
430
dhrumil
D
T
Atom HDL
Replies
12
Views
772
Paul Taylor
P
?
wait states
Replies
1
Views
392
Ralf Hildebrandt
R
A
Include file extension: ".v" vs ".vh"?
Replies
4
Views
454
Petter Gustad
P
K
Code not being simulated by Modelsim
Replies
4
Views
416
Jonathan Bromley
J
E
LRM expression definition oddities?
Replies
3
Views
412
-
?
L
Parameters of Parameters
2
Replies
21
Views
777
lingwitt
L
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