Verilog Language

V
Parellel simulation rus for regression in cadence xcelium
Replies
0
Views
392
Vijay
V
R
What use is the 3 delay number: min:typical:max?
Replies
2
Views
843
unfrostedpoptart
U
R
Question about 8'bx etc.
Replies
1
Views
855
Amolak Singh
A
Q
Asynchronous FIFO
Replies
2
Views
1K
Richard Damon
R
R
Does the parameter 'width' take effect in the called module?
Replies
1
Views
833
Gabor
G
Q
verilog syntax error
Replies
1
Views
857
-
?
R
Is ' wen_dly <= #TCQ 1'b0;' synthesisable?
Replies
4
Views
991
Kevin Neilson
K
R
What does '->' mean in this code snippet?
Replies
3
Views
909
unfrostedpoptart
U
?
replicating libre-licensed multiplexed tri-state pullup/pull
Replies
3
Views
915
-
?
B
Help with selfcheck TB
Replies
0
Views
321
BM
B
?
Purpose of a | (a ^ a)
Replies
2
Views
915
Allan Herriman
A
G
Asynchronous FIFO with depth that is not a power of 2
Replies
6
Views
2K
Kevin Neilson
K
A
Disable/enable PSL assertions
Replies
1
Views
1K
-
?
B
Request for an example in verilog testbench
Replies
0
Views
351
Bitan Mallik
B
S
how to simulate verilog with rom in modelsim?
Replies
9
Views
2K
-
?
Y
[discuss] verilog code to synthesis
Replies
4
Views
2K
-
?
?
A script to run a test bench on hundreds of student verilog
Replies
0
Views
386
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?
B
Ask about free access for synopsys vcs_mx_2016.03 or synopsy
Replies
0
Views
466
Bima Sahbani
B
E
Difference between Generate-for and for
Replies
5
Views
2K
rickman
R
I
SystemVerilog - integer range 0 to 9
Replies
6
Views
1K
rickman
R
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