FPGA

D
PCI interface with attached PLD
Replies
9
Views
563
Nial Stewart
N
P
verification vs validation
Replies
4
Views
498
Ian Poole
I
J
Aurora_401 reference allows 8B/10B bypass?
Replies
2
Views
452
Marc Randolph
M
J
Memory Initialization: mif, coe, hex, etc,
Replies
8
Views
784
H. Peter Anvin
H
M
Is this a good starter kit?
Replies
11
Views
818
Mike Silva
M
E
Altera Stratix synthesis error
Replies
2
Views
488
erojr
E
F
Xlilinx (xc2vp30-5fg676)
Replies
3
Views
471
Philip Freidin
P
S
Generating core using .mif file
Replies
0
Views
245
sree
S
D
Apex power calculator
Replies
2
Views
537
Ben Twijnstra
B
M
Xilinx WebPack and Linux/WINE
Replies
1
Views
465
Uwe Bonnes
U
V
Quartus II Node Finder
Replies
1
Views
476
Subroto Datta
S
P
Implementing submodules with their own constraint files
Replies
0
Views
287
PM
P
A
Small PLD choices
Replies
7
Views
701
Dan
D
M
FC II & Generic
Replies
0
Views
267
Marek Ponca
M
P
regarding clock routing
Replies
5
Views
578
Muthu
M
S
Undocumented units in Virtex (I assume in Spartan-II too)
Replies
1
Views
392
Sean Durkin
S
S
Virtex2Pro Internal Config. Access Port
Replies
0
Views
240
Silvano Bettinzana
S
W
Altera Max 7000 cpld's
Replies
2
Views
555
Wing Fong Wong
W
A
Does anyone know anything about DC-FPGA?
Replies
1
Views
413
Jay
J
R
Xilinx microblaze : SRAM external mem controller
Replies
3
Views
684
Goran Bilski
G
You must log in or register to post here.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top