FPGA

P
verification vs validation
Replies
4
Views
464
Ian Poole
I
J
Aurora_401 reference allows 8B/10B bypass?
Replies
2
Views
415
Marc Randolph
M
J
Memory Initialization: mif, coe, hex, etc,
Replies
8
Views
740
H. Peter Anvin
H
M
Is this a good starter kit?
Replies
11
Views
760
Mike Silva
M
E
Altera Stratix synthesis error
Replies
2
Views
441
erojr
E
F
Xlilinx (xc2vp30-5fg676)
Replies
3
Views
440
Philip Freidin
P
S
Generating core using .mif file
Replies
0
Views
216
sree
S
D
Apex power calculator
Replies
2
Views
497
Ben Twijnstra
B
M
Xilinx WebPack and Linux/WINE
Replies
1
Views
420
Uwe Bonnes
U
V
Quartus II Node Finder
Replies
1
Views
437
Subroto Datta
S
P
Implementing submodules with their own constraint files
Replies
0
Views
245
PM
P
A
Small PLD choices
Replies
7
Views
616
Dan
D
M
FC II & Generic
Replies
0
Views
231
Marek Ponca
M
P
regarding clock routing
Replies
5
Views
531
Muthu
M
S
Undocumented units in Virtex (I assume in Spartan-II too)
Replies
1
Views
360
Sean Durkin
S
S
Virtex2Pro Internal Config. Access Port
Replies
0
Views
217
Silvano Bettinzana
S
W
Altera Max 7000 cpld's
Replies
2
Views
505
Wing Fong Wong
W
A
Does anyone know anything about DC-FPGA?
Replies
1
Views
373
Jay
J
R
Xilinx microblaze : SRAM external mem controller
Replies
3
Views
656
Goran Bilski
G
V
CPLD : Generating reset signal
Replies
6
Views
577
Arthur
A
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