FPGA

A
Simulating multi-chip design
Replies
1
Views
377
Mario Trams
M
B
V2Pro floating point
Replies
1
Views
388
Valentino
V
K
Conversion of NCD files from 5.X to 6.1X, problem.
Replies
0
Views
189
Kelvin @ SG
K
K
Where do XPP290 places top-level logic when all three AREA_G
Replies
0
Views
188
Kelvin @ SG
K
T
readback spartan2e
Replies
1
Views
392
Chen Wei Tseng
C
C
[newbie] How to get the value of active pins through JTAG
Replies
0
Views
189
C...T
C
L
Spartan3 availability
2
Replies
38
Views
2K
Ralph Malph
R
J
VirtexE DLL locked range
Replies
1
Views
356
Austin Lesea
A
A
Adding internal signals in MODELSIM
Replies
5
Views
655
Mike Treseler
M
B
fast mod (remainder) algorithm for V2?
Replies
2
Views
394
Mike Treseler
M
N
Installation of Xlinx
Replies
2
Views
421
valentin tihomirov
V
M
Hyperthreading vs. Dual proc
Replies
12
Views
764
Martin Thompson
M
O
Xilinx Logicore PCI64 Problem
Replies
6
Views
493
owner
O
A
Winterschool on Embedded Systems (call for participation)
Replies
0
Views
185
Andy D. Pimentel
A
J
Followup to those that downloaded SeaHDL/SimHDL
Replies
0
Views
179
joe
J
J
connecting tristates
Replies
1
Views
386
Paulo Dutra
P
S
Release of SPARK C-to-VHDL Parallelizing High Level Synthesi
Replies
0
Views
179
S Gupta
S
J
Altera CPLD - Illegal assignment-global clock
Replies
2
Views
411
Dejan Durdenic
D
T
v2px70 available?
Replies
0
Views
184
T. Irmen
T
J
dynamic memory allocation NIOS
Replies
1
Views
402
Jesse Kempa
J
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