FPGA

R
Verilog and VHDL mix
Replies
4
Views
415
Allan Herriman
A
S
Do Xilinx Fix Their Prices?
2 3 4
Replies
74
Views
2K
Tim
T
M
Programming an EPC1 conf.Dev. from Altera
Replies
6
Views
471
Dejan Durdenic
D
K
Error in NetGen, "ATAL_ERROR:Anno:Engine.c:476:1.44 - Xdm Ex
Replies
0
Views
111
Kelvin @ SG
K
A
How many PCB layers ?
Replies
12
Views
818
William Wallace
W
T
Sensible starter FPGA board
Replies
7
Views
475
Alex Gibson
A
L
Spartan-3 shipping, or perhaps not!
Replies
9
Views
275
Valeri Serebrianski
V
P
regarding opto isolators
Replies
5
Views
379
Antti Lukats
A
D
Programmable clock, FPGA PLLs, and Actel PLL Core
2
Replies
24
Views
877
Marius Vollmer
M
I
Artificial Intelligence/FPGA
Replies
5
Views
920
nntp
N
S
Sine Wave Generation
Replies
8
Views
394
Martin Ryba
M
C
LVDS on Spartan 3
Replies
0
Views
117
Chris Cheung
C
L
APEX fit problem
Replies
1
Views
309
Jesse Kempa
J
K
is this enable structure ok for synthesis/high speed?
Replies
2
Views
280
Ken
K
G
Using DLL "locked" output as a global reset signal ?
Replies
1
Views
226
Austin Lesea
A
F
ISE 6.1.03i Linux...
Replies
1
Views
293
Andrew Greensted
A
M
xsa-50 board
Replies
1
Views
313
Dave Vanden Bout
D
J
Partial reconfig flow
Replies
9
Views
362
Sean Durkin
S
A
Use of memory bits in QuartusII
Replies
0
Views
116
ALuPin
A
K
timing constraints and enables
Replies
1
Views
307
Ken
K
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