FPGA

J
Basic jitter from a CPLD (XC7500XL)
Replies
15
Views
767
Jim
J
J
Question: size of Stratix??
Replies
1
Views
292
marise
M
M
How would you...
Replies
3
Views
317
Kevin Neilson
K
V
ngd2edif vs. ngc2edif
Replies
3
Views
367
Brian Philofsky
B
N
Suggestions
Replies
0
Views
109
naveen
N
H
VHDL FSM Problem
Replies
3
Views
310
pascal
P
H
one more inquiry....fpga architecture
Replies
2
Views
268
fabbl
F
J
altera, xilinx susceptible to power transients?
Replies
6
Views
354
Ray Andraka
R
C
Automatic Placement algorithm, help needed
Replies
1
Views
244
Paul E. Black
P
C
How to work with global clocks and buffers in CPLD?
Replies
0
Views
118
Chris Carlen
C
T
DCM Simulation Error
Replies
3
Views
349
Jakab Tanko
J
V
Modular Design in WebPack
Replies
2
Views
293
John Adair
J
T
powerpc
Replies
0
Views
115
Terrence Mak
T
D
ModelSim, Virtex DCM, and clk0 phase problem
Replies
1
Views
292
Brian Philofsky
B
P
ARM+FPGA tiny board
Replies
0
Views
110
Pablo Bleyer Kocik
P
A
SRAM bidirectional bus
Replies
3
Views
295
Michael Schöberl
M
K
Warning on DCM min frequency...
Replies
1
Views
295
Austin Lesea
A
J
Example using a custom OPB slave core with and interrupt
Replies
0
Views
112
Jeremy
J
S
An old FPGA paper back to 1986...
Replies
1
Views
273
fabbl
F
C
quartussII 3.0 , block editor, how to connect signals of bus
Replies
2
Views
234
chi
C
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