FPGA

K
16->5 "Sort"
2
Replies
23
Views
3K
Kevin Neilson
K
R
Open source Verilog BCH encoder/decoder
Replies
9
Views
1K
Russell Dill
R
C
synthesis tool for systemc
Replies
5
Views
981
Tim Wescott
T
J
Spartan-3 stater kit
Replies
9
Views
1K
BobH
B
F
Choosing the right FPGA board
Replies
10
Views
2K
FrewCen
F
?
Interested in VHDL and FPGA Development?
Replies
0
Views
252
-
?
G
Directly connect two XAUI ports inside FPGA
Replies
3
Views
851
Guenther Wenninger
G
W
Does each core of 8-core Intel processor has an independent
Replies
1
Views
632
Hendrik van der Heijden
H
H
Xilinx Aurora link splitter
Replies
2
Views
915
Hendrik van der Heijden
H
C
FPGA / DSP - Urgent need in Orange County, CA
Replies
1
Views
810
bobpainter
B
R
Division by a constant
Replies
10
Views
1K
Nikolaos Kavvadias
N
P
Aurora IP 8B10B problem with TVALID
Replies
0
Views
280
ponnagantiraju
P
E
Call for Participation: ACM/IEEE Symposium on Architectures
Replies
0
Views
273
Eric Keller
E
P
Microblaze with AXI streaming interfaces
Replies
0
Views
278
pad007
P
F
Question about summation function
Replies
1
Views
775
KJ
K
O
Graduate Research Assistantship at the Computer Systems Lab,
Replies
0
Views
281
Olufemi Adeluyi
O
?
Intel in Talks to buy Altera
2
Replies
28
Views
2K
-
?
A
looking for systemC/TLM 2.0 courses
Replies
11
Views
1K
-
?
N
Interpret a VHDL statement within a serial to paralell port
Replies
6
Views
987
rickman
R
A
Bad condition in wait statement, or only one clock per proce
Replies
1
Views
692
Brian Drummond
B
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