FPGA

R
Finally! I figgured it out accidentally....
Replies
2
Views
705
Rick C
R
K
Is there a way in Verilog to refer to a slice of an array?...
Replies
0
Views
572
Kevin Simonson
K
R
HP \"owning\" the software for Xilinx-FTDI drivers???...
Replies
6
Views
976
Rick C
R
U
ready/valid vs 2-way handshaking vs 4-way handshaking...
Replies
4
Views
781
Kevin Neilson
K
R
Active-HDL Throws Error...
Replies
14
Views
1K
HT-Lab
H
R
Gowin Synthesis Software...
Replies
0
Views
605
Rick C
R
S
adding FPGA grounds...
Replies
15
Views
1K
Rick C
R
K
What is wrong with low level code?...
Replies
14
Views
1K
Kevin Neilson
K
R
XLNX on the Auction Block?...
Replies
0
Views
521
Rick C
R
R
Real Time Simulation...
Replies
4
Views
618
HT-Lab
H
J
Piplineing logic alot? I have a tool for you...
Replies
0
Views
580
Julian Kemmerer
J
P
Multi-FPGA Interconnection: latest techniques...
Replies
9
Views
1K
Theo
T
K
How powerful is Verilog at using parameters to specify designs?...
2
Replies
21
Views
2K
Kevin Simonson
K
R
Active HDL Entity Retention...
Replies
4
Views
837
Rick C
R
S
FPGA sensitivities...
Replies
1
Views
555
Rick C
R
K
Is there any way to get a different font for code sections?...
Replies
1
Views
507
Rick C
R
M
Exponential Regression by XSG...
Replies
0
Views
511
Mjzoob I. Ibrahim
M
R
Gowin FPGA Oddities...
2
Replies
27
Views
3K
Rick C
R
M
exponential regression in XSG...
Replies
1
Views
539
Kevin Neilson
K
K
Is it illegal to use an (enum) as a Verilog function input?...
Replies
1
Views
566
gtwrek
G
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