Cadence

P
how to run VHDL-AMS Simulation in Cadence
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3
Views
1K
Andrew Beckett
A
?
Turn on all warnings from spectre in ade
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1
Views
441
Andrew Beckett
A
J
Global nets
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1
Views
499
Andrew Beckett
A
L
Thanks all buddies in this group!!!
Replies
0
Views
163
Lee
L
S
Background simulation of the Spectre
Replies
4
Views
600
Erik Wanta
E
E
AMS Designer tcl script mode determination?
Replies
1
Views
527
Andrew Beckett
A
S
Background simulation of the Spectre
Replies
2
Views
769
Andrew Beckett
A
M
Parameterized Verilog and long-module names in Ambit/PKS
Replies
0
Views
168
mwrew
M
L
Can I do LVS between gate netlist and transistor netlist in
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1
Views
500
Diva Physical Verificatio
D
L
"undefined function: avSwitch" error during LVS in Diva????
Replies
3
Views
561
Kholdoun TORKI
K
F
is tools/dfII/bin/nfsUpdate really useful ?
Replies
1
Views
471
Andrew Beckett
A
C
verilog-A
Replies
1
Views
537
Andrew Beckett
A
F
is tools/dfII/bin/nfsUpdate really useful ?
Replies
1
Views
573
Andrew Beckett
A
C
verilog-A
Replies
1
Views
500
Andrew Beckett
A
F
Analog artist resize - version 1.2.3
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0
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145
fogh
F
F
Analog artist resize - version 1.2.3
Replies
0
Views
307
fogh
F
L
Back-annotation for PrimeTime and power compiler in Synopsys
Replies
0
Views
179
Lee
L
B
mouseAddPt() force
2
Replies
23
Views
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Bob Moore
B
J
One of My High Technology Contributions to Microchip Design
2 3 4
Replies
62
Views
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Michael A. Covington
M
L
DRC in Virtuoso????
Replies
5
Views
678
Diva Physical Verificatio
D
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