M
mnentwig
Guest
Hi,
this is a "public backup" of a holiday project maybe it's of use t
someone:
https://drive.google.com/file/d/0B1gLUU8hXL7veXVmZDhURGJ0N3c/edit?usp=sharing
- "medium" ZPU processor
- instantiated BRAM and upload of program code via DATA2MEM. Re-compilin
the C-code and uploading a new bitstream takes about three seconds, whic
isn't too bad (I use Xilinx' platform cable USB; the Saturn V3 should als
support xc3sprog upload by itself)
- basic LPDRAM access as "proof-of-concept" using the Xilinx DRA
controller
- basic VGA, connect with Dupont wires to an analog RGB monitor input
- timing is met at the default 100 MHz clock
- address decoder with support for zero-waitstate reads (i.e. from hardwar
registers)
- performance is almost 1M 32-bit read/writes from DRAM per second, thre
times faster in internal BRAM. A speed demon in slow motion...
- 9 % slice utilization (6 % LUT) on Spartan 6 LX45
---------------------------------------
Posted through http://www.FPGARelated.com
this is a "public backup" of a holiday project maybe it's of use t
someone:
https://drive.google.com/file/d/0B1gLUU8hXL7veXVmZDhURGJ0N3c/edit?usp=sharing
- "medium" ZPU processor
- instantiated BRAM and upload of program code via DATA2MEM. Re-compilin
the C-code and uploading a new bitstream takes about three seconds, whic
isn't too bad (I use Xilinx' platform cable USB; the Saturn V3 should als
support xc3sprog upload by itself)
- basic LPDRAM access as "proof-of-concept" using the Xilinx DRA
controller
- basic VGA, connect with Dupont wires to an analog RGB monitor input
- timing is met at the default 100 MHz clock
- address decoder with support for zero-waitstate reads (i.e. from hardwar
registers)
- performance is almost 1M 32-bit read/writes from DRAM per second, thre
times faster in internal BRAM. A speed demon in slow motion...
- 9 % slice utilization (6 % LUT) on Spartan 6 LX45
---------------------------------------
Posted through http://www.FPGARelated.com