Zero width concatenation.

[Ron Smith]

The verilog spec does not define any limits on the value for the
replication operator in concatenation.

So is the following well behaved?

{0{1'b1}};

The real intent of this is to support the following:

parameter WIDE=5; // instantiation parameter between 1 and 16

wire [WIDE-1:0] mywire;
wire [15:0] otherwire;
wire [31:0] mybus;

assign mybus={otherwire,{16-WIDE{1'b0}},mywire};

If you make mywire its maximum width, it does not need any zero padding,
so this should degenerate to a zero width bus, i.e. nothing.

I wrote a test case, and it *seems* to work, but its a long way between
working verilog and working silicon... So I want to see if anybody has
done this successfully through the entire tool chain.

 

[Swapnajit Mittra]

Ron Smith <rdsmith@sedona.intel.com> wrote in message news:<bn977r$ugr$1@news01.intel.com>...

The verilog spec does not define any limits on the value for the
replication operator in concatenation.

So is the following well behaved?

{0{1'b1}};

The real intent of this is to support the following:

parameter WIDE=5; // instantiation parameter between 1 and 16

wire [WIDE-1:0] mywire;
wire [15:0] otherwire;
wire [31:0] mybus;

assign mybus={otherwire,{16-WIDE{1'b0}},mywire};

If you make mywire its maximum width, it does not need any zero padding,
so this should degenerate to a zero width bus, i.e. nothing.

I wrote a test case, and it *seems* to work, but its a long way between
working verilog and working silicon... So I want to see if anybody has
done this successfully through the entire tool chain.

Synopsys dc_shell did not complain, though YMMV
based on what synthesizer you are using.

- Swapnajit.

=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/

 

[ABW]

"Ron Smith" <rdsmith@sedona.intel.com> wrote in message
news:bn977r$ugr$1@news01.intel.com...

The verilog spec does not define any limits on the value for the
replication operator in concatenation.

Verilog '95 does not, but Verilog 2001 does. There is a small error in spec.

so look directly here:
http://www.boyd.com/1364_btf/report/full_pr/76.html

Your intent is clear however there are two problems:
1) parameter = {0{1'b1}}; - what should be the width and value of such
parameter?
2) I've checked your example on couple of simulators - they simulate it
however not the way you expect (well, one actually simulates it the way you
wanted). VCSi gives clear warning on this:
Warning-[ZONMCM] Zero or negative multiconcat multiplier
"test2.v", 30: {(16 - WIDE) {1'b0}}
this will be replaced by 1'b0
In case of WIDE == 16 simulators behave as if you had:
assign mybus={otherwire,1'b0,mywire};
(effectively the same as for WIDE==15) and you expected:
assign mybus={otherwire,mywire};

Maybe you can use:
assign mybus={ otherwire , ( 16'b0 | mywire ) };
Unfortunately all high impedance bits in mywire will turn into unknowns if
you use the above.
If you want z's in mywire to be assigned unchanged and you want your code to
be fully LRM compliant you may need the following monster ) :
assign mybus= WIDE==16 ? {otherwire,mywire}:
{otherwire,{WIDE==16?1:16-WIDE{1'b0}},mywire};

Is there an easier way to achieve the same (padding with zeros for WIDE<16,
passing z's unchanged and full LRM compliance)?