Zero-drift amplifiers with negative PSRR

Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 180mV down for
60us. Repeat.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Cheers,
James Arthur

 

On Sunday, October 6, 2019 at 1:53:47 PM UTC-4, jla...@highlandsniptechnology.com wrote:

On Sun, 6 Oct 2019 10:23:52 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 160mV down for
60us. Repeat.

I'm having that problem too, on a 1 volt supply for an FPGA core. I'm
trying to get the kids to spin up a bunch of MACs or something, to use
more current and stop the switcher from burping. I'm getting 6 ps RMS
jitter and I want less; I blame the power supply.

At these current levels, use a linear reg! Or RC filter the amp supply
hard.

I bodged in a 270uH inductor for the moment, which does a surprisingly
good job. But yes, there's an LDO in this circuit's future.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Looks like that amp chops at 1 KHz, so it could be beating with the
supply. But then, the CMRR (fig 21) is all-by-itself terrible at even
1 KHz.

That's an excellent point. Since it's a unity-gain buffer, the
problem here is really CMRR, not PSRR.

We use some opamps with PSRR that has actual gain at some frequencies.

I think people tend to design elegant low-noise circuits, and then
power them from noisy supplies.

No kidding. Elsewhere, this design was using the ripply 3.3v rail
as Vref!

--
John Larkin Highland Technology, Inc

lunatic fringe electronics

Cheers,
James

 

On Sun, 6 Oct 2019 10:23:52 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 180mV down for
60us. Repeat.

I'm having that problem too, on a 1 volt supply for an FPGA core. I'm
trying to get the kids to spin up a bunch of MACs or something, to use
more current and stop the switcher from burping. I'm getting 6 ps RMS
jitter and I want less; I blame the power supply.

At these current levels, use a linear reg! Or RC filter the amp supply
hard.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Cheers,
James Arthur

Looks like that amp chops at 1 KHz, so it could be beating with the
supply. But then, the CMRR (fig 21) is all-by-itself terrible at even
1 KHz.

We use some opamps with PSRR that has actual gain at some frequencies.

I think people tend to design elegant low-noise circuits, and then
power them from noisy supplies.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

On Sunday, October 6, 2019 at 2:48:16 PM UTC-4, Winfield Hill wrote:

dagmargoodboat@yahoo.com wrote...

I bodged in a 270uH inductor for the moment ...

Do you really need the 0.65uA supply current?

No, I don't. In fact I don't even need the buffers -- I'm
not sure why the previous gent felt we needed them. They buffer
against a little kick-out charge from the a/d, but an existing
filtering cap should suppress that error just fine. Replacing the
buffer amps with jumpers would eliminate this one PSRR problem
completely. (And save 3 x 650 nA!

But boards not in my possession have to be installed and in
service in a few days, so changes are inconvenient. The inductor
easily drops in to replace a two-pin power-supply-isolating
shunt that the previous designer thoughtfully provided.

The real solution, of course, is an LDO.

> A higher supply current op-amp would work better.

Yep.

--
Thanks,
- Win

Cheers,
James Arthur

 

[Uwe Bonnes]

jlarkin@highlandsniptechnology.com wrote:
....

At these current levels, use a linear reg! Or RC filter the amp supply
hard.



Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

At Icc=650nA, RC filter seems resonable. I like to use
L (ferriter bead)/ C
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------

 

[Winfield Hill]

dagmargoodboat@yahoo.com wrote...

I bodged in a 270uH inductor for the moment ...

Do you really need the 0.65uA supply current?
A higher supply current op-amp would work better.


--
Thanks,
- Win

 

On Sun, 6 Oct 2019 11:14:57 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Sunday, October 6, 2019 at 1:53:47 PM UTC-4, jla...@highlandsniptechnology.com wrote:
On Sun, 6 Oct 2019 10:23:52 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 160mV down for
60us. Repeat.

I'm having that problem too, on a 1 volt supply for an FPGA core. I'm
trying to get the kids to spin up a bunch of MACs or something, to use
more current and stop the switcher from burping. I'm getting 6 ps RMS
jitter and I want less; I blame the power supply.

At these current levels, use a linear reg! Or RC filter the amp supply
hard.

I bodged in a 270uH inductor for the moment, which does a surprisingly
good job. But yes, there's an LDO in this circuit's future.

At your current levels, you could filter the supply with an RC with a
1 second time constant.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Looks like that amp chops at 1 KHz, so it could be beating with the
supply. But then, the CMRR (fig 21) is all-by-itself terrible at even
1 KHz.

That's an excellent point. Since it's a unity-gain buffer, the
problem here is really CMRR, not PSRR.

Depends on the precise definition of CMRR. At 1 KHz, the CMRR of that
part is about 70 dB worse than the PSRR.

It's unfortunate that opamps don't have ground pins. All the internal
guts are hung off the power supplies.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

On Sunday, October 6, 2019 at 1:23:55 PM UTC-4, dagmarg...@yahoo.com wrote:

Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 180mV down for
60us. Repeat.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Cheers,
James Arthur

PSR is input-referred, of course, and so is much worse at higher gains.

Cheers

Phil Hobbs

 

On Sunday, October 6, 2019 at 3:36:34 PM UTC-4, Uwe Bonnes wrote:

jlarkin@highlandsniptechnology.com wrote:
...

At these current levels, use a linear reg! Or RC filter the amp supply
hard.



Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

At Icc=650nA, RC filter seems resonable. I like to use
L (ferriter bead)/ C
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------

Alas, I've got other beasties to feed of this rail, and they're
much hungrier. Using an r-c- might apply at revision time, when I could
separate those few devices from the power plane and filter them
specifically. But I'm more likely to take them out completely,
saving power, parts, and improving accuracy too.

Cheers,
James Arthir

 

On Sunday, October 6, 2019 at 3:47:27 PM UTC-4, jla...@highlandsniptechnology.com wrote:

On Sun, 6 Oct 2019 11:14:57 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Sunday, October 6, 2019 at 1:53:47 PM UTC-4, jla...@highlandsniptechnology.com wrote:
On Sun, 6 Oct 2019 10:23:52 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 160mV down for
60us. Repeat.

I'm having that problem too, on a 1 volt supply for an FPGA core. I'm
trying to get the kids to spin up a bunch of MACs or something, to use
more current and stop the switcher from burping. I'm getting 6 ps RMS
jitter and I want less; I blame the power supply.

At these current levels, use a linear reg! Or RC filter the amp supply
hard.

I bodged in a 270uH inductor for the moment, which does a surprisingly
good job. But yes, there's an LDO in this circuit's future.

At your current levels, you could filter the supply with an RC with a
1 second time constant.

I can't. These buffers run all the time and draw nothing. But
other loads intermittently draw ~120-ish mA off the same rail.
270uH with 20uF makes a 2kHz filter. That knocked most of the
piss out of it.

Easiest and most accurate is just to remove the buffers.

They're really unnecessary, too slow and hi-z to compensate the a/d's
charge kick-out anyhow. But the same opamp might be handy elsewhere,
when I revise the board.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Looks like that amp chops at 1 KHz, so it could be beating with the
supply. But then, the CMRR (fig 21) is all-by-itself terrible at even
1 KHz.

That's an excellent point. Since it's a unity-gain buffer, the
problem here is really CMRR, not PSRR.

Depends on the precise definition of CMRR. At 1 KHz, the CMRR of that
part is about 70 dB worse than the PSRR.
|\
----R1----+----+------|+\

| C1 | | >-+-->
R2 --- .--|-/ |
| --- | |/ |
=== | '-------'
===

Well, if a unity-gain follower's rail bounces and one input stays
fixed, the part sees the rail bounce as a common mode input, right?

Any chopper that's alternately sampling its inputs will see
a slewing common mode voltage as a differential mode signal.

Yet another proof for Larkin's Law of Op Amps: Always invert.
(Except I can't, here.)

It's unfortunate that opamps don't have ground pins. All the internal
guts are hung off the power supplies.

Cheers,
James Arthur

 

On Sunday, October 6, 2019 at 7:33:30 PM UTC-4, pcdh...@gmail.com wrote:

On Sunday, October 6, 2019 at 1:23:55 PM UTC-4, dagmarg...@yahoo.com wrote:
Just a little heads-up: I'm working on someone's
design that has LPV821's. It's a nano-power
zero-drift amp with incredible offset specs, being
used as a unity-gain d.c. buffer.

http://www.ti.com/lit/ds/symlink/lpv821.pdf

The amp's input is clean, but its output has 180mV
shark's fins superimposed on the d.c. level.

The culprit? PSRR. The 3.3v supply, generated by a
burst-mode micropower switcher, makes a rail that
slews ~160mV up in 10us, then coasts 180mV down for
60us. Repeat.

Cleaning the rail removes the shark's fins. But I can
see why the designer didn't think he needed to -- the
LPV821's Fig. 22 says PSRR @ 100kHz should be >80dB.
But at this slightly-faster frequency, I'm seeing
PSRR = 20log(160mV/180mV) = -1db.

My most charitable explanation: the rail frequency must
be aliasing with the amp's zero-drift circuitry in some
unfortunate way.

Otherwise, it's a lovely part. Icc=650nA, Vos<10uV.

Cheers,
James Arthur

PSR is input-referred, of course, and so is much worse at higher gains.

Cheers

Phil Hobbs

Right, so if I'd had an inverting unity-gain amplifier with
zero CMV, 160mV on the rail suppressed by 70dB PSRR should've
made <calculates furiously> 50uV on the output.

Instead I'm getting 180mV, thus diverting attention to the
most-worse CMRR, instead.

Cheers,
James Arthur