E
Espen Tallaksen
Guest
- and that also includes preparing the use of any UVVM Utility Library command available, - for logging, checking signal values and signal stability, waiting for signal changes, values or stability, clock generation, synchronization, and lots of other very useful testbench functionality.
The *exhaustive* list of what to do:
1. Download from Github https://github.com/UVVM/UVVM
2. Compile Utility Library as follows:
a) Inside your simulator go to âuvvm_util/simâ
b) execute: âsource ../script/compile_src.doâ
3. Include the library inside your testbench by adding the following lines before your testbench entity declaration:
library uvvm_util;
context uvvm_util.uvvm_util_context;
4. You may now enter any utility library command inside your testbench processes (or subprograms)
e.g. log("Hello world");
----
You find a full Quick reference for all these commands inside the download (or here: https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/util_quick_ref.pdf). This includes a command overview - followed by detailed info per command - including type overloads, description and examples.
Invest another 4 minutes and you are ready to run your first high level transaction commands on AXI4-lite, AXI4-stream, Avalon, SPI, I2C, UART and more. All you need to do is to compile and include the relevant Verification IP (e.g. bitvis_vip_uart) in the same way as for bullets 2 and 3 above, and then just execute any UART transaction command as given in the relevant quick reference (e.g. uart_transmit(x"5A", "Transmitting my first byte", clk, tx);
UVVM is the fastest growing FPGA (and ASIC) verification methodology world-wide (acc. to Wilson Research). Invest 4 minutes and get started now. (There is plenty documentation on Github. Check out the README file for more info and links to Powerpoints, Documentation, Webinars, etc..
The *exhaustive* list of what to do:
1. Download from Github https://github.com/UVVM/UVVM
2. Compile Utility Library as follows:
a) Inside your simulator go to âuvvm_util/simâ
b) execute: âsource ../script/compile_src.doâ
3. Include the library inside your testbench by adding the following lines before your testbench entity declaration:
library uvvm_util;
context uvvm_util.uvvm_util_context;
4. You may now enter any utility library command inside your testbench processes (or subprograms)
e.g. log("Hello world");
----
You find a full Quick reference for all these commands inside the download (or here: https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/util_quick_ref.pdf). This includes a command overview - followed by detailed info per command - including type overloads, description and examples.
Invest another 4 minutes and you are ready to run your first high level transaction commands on AXI4-lite, AXI4-stream, Avalon, SPI, I2C, UART and more. All you need to do is to compile and include the relevant Verification IP (e.g. bitvis_vip_uart) in the same way as for bullets 2 and 3 above, and then just execute any UART transaction command as given in the relevant quick reference (e.g. uart_transmit(x"5A", "Transmitting my first byte", clk, tx);
UVVM is the fastest growing FPGA (and ASIC) verification methodology world-wide (acc. to Wilson Research). Invest 4 minutes and get started now. (There is plenty documentation on Github. Check out the README file for more info and links to Powerpoints, Documentation, Webinars, etc..