You can improve the performance of the multiplier Mmult__mul

[Nevo]

When synthesizing my Verilog project in XST, I get the following INFO
message:

Synthesizing (advanced) Unit <ClockGenerator>.
Found pipelined multiplier on signal <_mult0000>:
- 1 pipeline level(s) found in a register connected to the multiplier
macro output.
Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the
multiplier Mmult__mult0000 by adding 1 register level(s).


I'm curious about the meaning of this message and how I might improve my
design.

Thanks,

-Nevo