Yet another newbie question

[Daniel]

Hi,

A question from a true newbie on Verilog 2001

- I need to initialize a variable (length 128 bits) with 16 bytes in
hexadecimal form to which I need to add a value. Can you pls
correct/confirm the following code:

data = 128'h000102030405060708090A0B0C0D0E0F
data = data + 2'b11 //Add binary (decimal value 3) to data
data = data + 'h0A //Add hexadecimal (decimal value 10) to data

Hope to read you soon,
Dan

 

[gabor]

On Oct 29, 12:49 pm, "Daniel" <> wrote:

Hi,

A question from a true newbie on Verilog 2001

- I need to initialize a variable (length 128 bits) with 16 bytes in
hexadecimal form to which I need to add a value. Can you pls
correct/confirm the following code:

data  = 128'h000102030405060708090A0B0C0D0E0F
data  = data + 2'b11 //Add binary (decimal value 3) to data
data  = data + 'h0A  //Add hexadecimal (decimal value 10) to data

Hope to read you soon,
Dan

Assuming these assignments are inside an initial or always block,
the only thing you need to add is semicolons at the end of each
line (but before the // comments).

 

[Matthew Hicks]

On Oct 29, 12:49 pm, "Daniel" <> wrote:

Hi,

A question from a true newbie on Verilog 2001

- I need to initialize a variable (length 128 bits) with 16 bytes in
hexadecimal form to which I need to add a value. Can you pls
correct/confirm the following code:

data = 128'h000102030405060708090A0B0C0D0E0F
data = data + 2'b11 //Add binary (decimal value 3) to data
data = data + 'h0A //Add hexadecimal (decimal value 10) to data
Hope to read you soon,
Dan
Assuming these assignments are inside an initial or always block, the
only thing you need to add is semicolons at the end of each line (but
before the // comments).

You would be better to do it all in one line, during declaration. You have
to make changes to do this in an combinational always block. You would need
a variable to hold the preliminary results of the first two statements because
data is an input to some of the assignments contained in the block. This
would create a feedback loop with behavior possibly different than what you
want.


---Matthew Hicks

 

[Daniel]

Thanks for the replies.

I have to place the code in an @always block and end each statement
with a semicolon (

I just wanted to know if the initialization of the variable 'data' is
ok and also if the way to add other values to this variable is
correctly declared (so it will eventually do the simple math).

Is there a carry/overflow like in assembler? I mean, what happens if I
declare a byte data = 8'b11111111 and add a value (like 'b1) to it?
Will the result be 00000000 or 100000000 ? My guess would be 00000000
as I only reserved 8 bits?

Hope to read you soon,
Daniel

 

[gabor]

On Oct 30, 1:12 am, "Daniel" <> wrote:

Thanks for the replies.

I have to place the code in an @always block and end each statement
with a semicolon (

I just wanted to know if the initialization of the variable 'data' is
ok and also if the way to add other values to this variable is
correctly declared (so it will eventually do the simple math).

Is there a carry/overflow like in assembler? I mean, what happens if I
declare a byte data = 8'b11111111 and add a value (like 'b1) to it?
Will the result be 00000000 or 100000000 ? My guess would be 00000000
as I only reserved 8 bits?

Hope to read you soon,
Daniel

You guessed right. The "result" of evaluating the right side of
an assignment would be extended to fit the answer, in your case
9'b100000000. Then the assignment takes the least significant
8 bits of the "result" and stuffs it into your 8-bit reg. Unlike
VHDL, there is no complaint in Verilog when the left and right
hand sides of an assignment have different widths.

You still need to watch out for implied widths when you are not
making an assignment to a sized register. For example if you
had written
reg [7:0] byte_data = 8'b1111111;

.. . .
if ((byte_data + 1) == 0)
.. . .

Then "byte_data + 1" evaluates to 9'b100000000 even though
that doesn't fit into byte_data. So the if condition would be
false.

HTH,
Gabor