Yet another newbie question

[lei]

Hi all:
When writing a module, an output port will be driven according to
some condition (in "if" or "case" statement). Suppose I have 32 port
to be driven. So I can't declare these port as "wire", only a "reg"
type would work? From synthesis point of view, what's the difference
between "reg" and "wire"? Does "reg" actually use a flip-flop and
"wire" doesn't ?
Is there any general guide line on when I should use "wire" and
when I should use "reg"? Besides the obvious restriction that "wire"
can't appear in procedure statement. After reviewing my module, I
found out that since i HAVE to use "if" and "case" , etc. So in what
cases that the "wire" type make more sense then "reg"?

Thanks
lei

 

[Jonathan Bromley]

On Wed, 28 May 2008 12:01:24 -0700 (PDT), lei <leisun124@gmail.com>
wrote:

Is there any general guide line on when I should
use "wire" and when I should use "reg"?

It's this easy (and there is no escape):

If you write to a thing using procedural code - in an
always or initial block, or in the body of a task or
function - then that thing MUST be a variable (reg).

EVERYTHING else MUST be a net (wire).

Nets get their value by any of...
- continuous assign statement: assign some_net = ...;
- because they're connected to the output port of a module,
and therefore are driven by continuous assignment from
inside the module
- because they are an input port of a module, and
therefore are driven by continuous assignment from
outside the module
and a few other, less common situations: notably, the
signals on both sides of an inout port (both inside the
module, and what you connect to the port outside it)
must be nets; and connections to outputs of Verilog
primitives or UDPs must be nets.

"reg" is by far the most common kind of variable,
but there are a few others - notably "integer".

"wire" is by far the most common kind of net, but
there are a few others - trireg, wand, wor... You
don't need to worry about them when you're starting
out with Verilog.

That's it. Easy to write down, but sometimes hard to
remember
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[glen herrmannsfeldt]

lei wrote:

When writing a module, an output port will be driven according to
some condition (in "if" or "case" statement). Suppose I have 32 port
to be driven. So I can't declare these port as "wire", only a "reg"
type would work? From synthesis point of view, what's the difference
between "reg" and "wire"? Does "reg" actually use a flip-flop and
"wire" doesn't ?

That sounds good, but it isn't how it works. I usually think
of reg as one that keeps its value, while wire needs a source
to keep its value. Wire is used for continuous assignment, like
connecting wires between real logic gates.

reg is used with behavioral logic, inside always blocks.
If you think of the statements as being executed sequentially,
it is reg that allows something to keep a value between
assignment. That is true even for combinatorial
(no register) logic.

Personally, I write structural model (continuous assignment
and connections between modules) for everything except
actual flip-flops. I might do a multiplexer in behavioral
logic (using case), it is a little easier than using ?:.

-- glen