Yet another "generate" question

M

Martin Euredjian

Guest
generate
for(i=0; i <= WIDTH; i=i+1) begin:BIT
if(i != WIDTH)begin:USELESS
myXOR2 x(.O(xor2), .I0(A), .I1(B));
MUXCY m(.O(cy[i+1]), .CI(cy), .DI(A), .S(xor2));
XORCY xc(.O(xorcy), .CI(cy), .LI(xor2));
FDRE f(.Q(SUM), .C(CLK), .CE(CE), .D(xorcy), .R(RST));
end
else begin:USELESS
FDRE f(.Q(SUM), .C(CLK), .CE(CE), .D(cy), .R(RST));
end
end
endgenerate

That should make an adder. No problem.

However, unless I'm missing something about the syntax, I can't seem to use
a simple if...else..then construct without a "begin:<identifier>" being
required. The above instantiates entities with names like:

BIT[0].USELESS.x
BIT[1].USELESS.x
BIT[2].USELESS.x
BIT[3].USELESS.x
....etc.

What I would love to see is:
BIT[0].x
BIT[1].x
BIT[2].x
BIT[3].x
....etc.

Where have I gone astray?

Thanks,


--
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Martin Euredjian

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Hi Martin,

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:pVshb.13436$Ba6.10331@newssvr25.news.prodigy.com...
generate
for(i=0; i <= WIDTH; i=i+1) begin:BIT
if(i != WIDTH)begin:USELESS
[...]
end
end
endgenerate

However, unless I'm missing something about the syntax, I can't seem to
use
a simple if...else..then construct without a "begin:<identifier>" being
required. The above instantiates entities with names like:

BIT[0].USELESS.x
...etc.

What I would love to see is:
BIT[0].x
...etc.

Where have I gone astray?
I don't think you have. My understanding is that generate...if..
doesn't require a block label, unlike generate...for...

I fleshed out your example with all the missing declarations and
modules, and ModelSim 5.7c happily compiled and elaborated it -
both with and without labels on the generate...if. Omitting the
mandatory label on the generate...for...begin yields an error,
as expected.

Which tool is complaining? It would be interesting to know...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
"Jonathan Bromley" wrote:

Which tool is complaining? It would be interesting to know...
XST.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
6.1i

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:6Tvhb.13441$GX6.4640@newssvr25.news.prodigy.com...
"Jonathan Bromley" wrote:

Which tool is complaining? It would be interesting to know...

XST.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:6Tvhb.13441$GX6.4640@newssvr25.news.prodigy.com...

Which tool is complaining? It would be interesting to know...

XST.
Don't you just feel a bug report coming on? :)

Hey, let's not complain too much. At least XST *understands* generate.
Lots of Verilog tools are only just getting there...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 

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