Yet again Blocking & Non Blocking

[Akhilesh Mritunjai]

Greetings

I have a few doubts, I would be grateful if anybody can shed some
light on them:

1. What does a blocking assignment get synthesized into ? I understand
how continuous assignment for combinational logic will work, but what
about procedural ones (eg blocking assignment in always block) ?

2. What I can make so far is that procedural blocking assignments are
meaningless and have no physical significance or hardware analogy. If
my assumption is correct, does it mean that synthesizer somehow
manages to convert blocking assignments into behaviourly same set of
non-blocking assignments (using/eliminating [additional] regs/wires) ?

I'd like to limit the scope to synthesizable subset of Verilog. I will
highly appreciate it if someone can shed light on differences between
1995, 2001 and SystemVerilog (1, 2, 3, ??) standards as well.

Thanks a lot

Regards
- Akhilesh Mritunjai

 

[John_H]

Blocking statements work fine and synthesize.
They just rarely have use in synthesized code.

A complex "for" loop is one place I've used the blocking operator, at least
in the days before Verilog2001. You can build up a variable based on itself
from the previous step in the loop without having to define intermediate
values yourself. The blocking statements just build up the final states of
the variables in the block sequentially rather than in parallel. Once
you've gotten to the end of the always block, the last assignments made to
those variables are what gets used.

Consider the code snip below (which I didn't bother to compile so it might
not be 100%) that provides an index for the most significant 1 on a 32-bit
value:

input [32:1] InBits;
integer i;
reg [5:0] MSB_one; // 0 means no 1s, 6'd32 is the MSbit
always @(posedge clk)
begin
MSB_one = 0; // if no 1s exist, this is the only statement encountered
for( i=1; i<=32; i=i+1 )
if( InBits == 1'b1 ) MSB_one = i; // previous value is overridden
end


"Akhilesh Mritunjai" <mritun@gmail.com> wrote in message
news:fdd37eda.0409292129.7d45fd78@posting.google.com...

Greetings

I have a few doubts, I would be grateful if anybody can shed some
light on them:

1. What does a blocking assignment get synthesized into ? I understand
how continuous assignment for combinational logic will work, but what
about procedural ones (eg blocking assignment in always block) ?

2. What I can make so far is that procedural blocking assignments are
meaningless and have no physical significance or hardware analogy. If
my assumption is correct, does it mean that synthesizer somehow
manages to convert blocking assignments into behaviourly same set of
non-blocking assignments (using/eliminating [additional] regs/wires) ?

I'd like to limit the scope to synthesizable subset of Verilog. I will
highly appreciate it if someone can shed light on differences between
1995, 2001 and SystemVerilog (1, 2, 3, ??) standards as well.

Thanks a lot

Regards
- Akhilesh Mritunjai