y i m geting this error

[dolly]

//this is module
module value1(v1_a,v1_n,v1_result);

input [15:0] v1_a,v1_n;
output v1_result;
reg [15:0] v1_result;
always @ (v1_a or v1_n)
v1_result= v1_a * v1_a * v1_a * v1_a;
endmodule

//this is the stimulus
module stimulus;

reg [15:0] a,n,b;
wire [15:0] v1_out;

value1 v1(a1,n1,v1_out);

initial
begin
a=10;
b= 10;
n= 4;

# 10

a=3;
b= 4;
n= 4;
end
endmodulue



in this code i m getting a 2 warnings that
1. port size dont match in port#1(16 vs 16)
2.port size dont match in port#1(16 vs 16)

tell me the reason

 

[John_H]

"dolly" <shehnaz.tariq@gmail.com> wrote in message
news:ebb7488f0b005a620084f2af861fa7d6@localhost.talkaboutprogramming.com...

//this is module
[snip]
output v1_result;
reg [15:0] v1_result;
[snip]
//this is the stimulus
[snip]
value1 v1(a1,n1,v1_out);

dimension your output...
output [15:0] v1_result;

and where do you assign a1 or n1 ?

 

[dolly]

i dun define a1 and n1 they are used in stimulus and are just a reference
and they are refrencing the module which is follows

module value1(v1_a,v1_n,v1_out);

input [15:0] v1_a,v1_n;
output v1_out;
reg [15:0] v1_out;
always @ (v1_a or v1_n)
v1_out= v1_a * v1_a * v1_a * v1_a;
endmodule

secondly if in place of
value1 v1(a1,n1,v1_out);
i wrote
value1 v1(v1_a,v1_n,v1_out);
it didnt make any difference im getting the same warning

and what u r saying if there is declaration problem i must get an "error"

 

[Andy Peters]

"dolly" <shehnaz.tariq@gmail.com> wrote in message news:<2052b8ecb2d6a56adbe77c825abebf8d@localhost.talkaboutprogramming.com>...

i dun define a1 and n1 they are used in stimulus and are just a reference
and they are refrencing the module which is follows

module value1(v1_a,v1_n,v1_out);

input [15:0] v1_a,v1_n;
output v1_out;
reg [15:0] v1_out;
always @ (v1_a or v1_n)
v1_out= v1_a * v1_a * v1_a * v1_a;
endmodule

secondly if in place of
value1 v1(a1,n1,v1_out);
i wrote
value1 v1(v1_a,v1_n,v1_out);
it didnt make any difference im getting the same warning

and what u r saying if there is declaration problem i must get an "error"

Your mistake is OBVIOUS.

You declare:

output vl_out;

and on the VERY NEXT LINE, you type,

reg [15:0] v1_out;

What is the difference between these two lines? THAT is your mistake.

-a