Guest
hi everyone.
i'm a newbe to verilog and fpga.
i'm trying to compile my first group of HDL programs.
but there are lots of trouble-some warnings that made me so tired.
some inputs of the verilog code are not included in the synthesis.
and just 14 out of 41 I/Os are shown in the compile results.
in this code i want to read 3 A/Ds and show their value in 4*20 char-
LCD.
can anybody help me to find out my mistakes
thanks in advance
here are the compile results
//-------------------------------------------------------------------------------------------------------
Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 1.00 s
--> Reading design: freerun.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options
Summary *
=========================================================================
---- Source Parameters
Input File Name : freerun.prj
Input Format : mixed
Ignore Synthesis Constraint File : NO
Verilog Include Directory :
---- Target Parameters
Output File Name : freerun
Output Format : NGC
Target Device : xc9500
---- Source Options
Top Module Name : freerun
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
Equivalent register Removal : YES
MACRO Preserve : YES
XOR Preserve : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
lso : freerun.lso
verilog2001 : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL
Compilation *
=========================================================================
Compiling source file "freerun.v"
Module <freerun> compiled
No errors in compilation
Analysis of file <freerun.prj> succeeded.
=========================================================================
* HDL
Analysis *
=========================================================================
Analyzing top module <freerun>.
WARNING:Xst:905 - freerun.v line 90: The signals <reset_done> are
missing in the sensitivity list of always block.
Module <freerun> is correct for synthesis.
=========================================================================
* HDL
Synthesis *
=========================================================================
Synthesizing Unit <freerun>.
Related source file is freerun.v.
WARNING:Xst:1306 - Output <lcd_en> is never assigned.
WARNING:Xst:1306 - Output <lcd_rs> is never assigned.
WARNING:Xst:646 - Signal <adc_reg1<7:6>> is assigned but never used.
WARNING:Xst:653 - Signal <lcd_data_reg> is used but never assigned.
Tied to value 00000000.
WARNING:Xst:646 - Signal <yekan> is assigned but never used.
WARNING:Xst:646 - Signal <hum_char> is assigned but never used.
WARNING:Xst:646 - Signal <char_gas> is assigned but never used.
WARNING:Xst:737 - Found 1-bit latch for signal <reset_done>.
WARNING:Xst:737 - Found 8-bit latch for signal <adc_reg1>.
WARNING:Xst:737 - Found 8-bit latch for signal <bin_temperature>.
WARNING:Xst:737 - Found 8-bit latch for signal <bin_temperature>.
WARNING:Xst:737 - Found 1-bit latch for signal <buzzer_reg>.
WARNING:Xst:737 - Found 4-bit latch for signal <dahgan>.
WARNING:Xst:737 - Found 4-bit latch for signal <sadgan>.
WARNING:Xst:737 - Found 1-bit latch for signal <continue_this_loop>.
Found 8-bit comparator greater for signal <$n0002> created at line
109.
Found 4-bit adder for signal <$n0004> created at line 111.
Found 8-bit comparator greater for signal <$n0005> created at line
102.
Found 4-bit adder for signal <$n0006> created at line 104.
Found 8-bit subtractor for signal <$n0008>.
Found 17-bit up counter for signal <adc_timer>.
Found 21-bit up counter for signal <lcd_timer>.
Found 9 1-bit 2-to-1 multiplexers.
Summary:
inferred 2 Counter(s).
inferred 3 Adder/Subtracter(s).
inferred 2 Comparator(s).
Unit <freerun> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that
some arithmetic operations in this design can share the same physical
resources for reduced device utilization. For improved clock frequency
you may try to disable resource sharing.
=========================================================================
* Advanced HDL
Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# Latches : 1
1-bit latch : 1
=========================================================================
=========================================================================
* Low Level
Synthesis *
=========================================================================
Optimizing unit <freerun> ...
=========================================================================
* Final
Report *
=========================================================================
Final Results
RTL Top Level Output File Name : freerun.ngr
Top Level Output File Name : freerun
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : xc9500
Macro Preserve : YES
XOR Preserve : YES
wysiwyg : NO
Design Statistics
# IOs : 41
Cell Usage :
# BELS : 3
# GND : 1
# INV : 2
# FlipFlops/Latches : 1
# LD : 1
# IO Buffers : 14
# IBUF : 2
# OBUF : 12
=========================================================================
CPU : 3.59 / 4.78 s | Elapsed : 4.00 / 5.00 s
-->
Total memory usage is 51104 kilobytes
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
// and this is my code
//
**********************************************************************************************
module
freerun(adc1,adc2,adc3,adc_wr1,adc_wr2,adc_wr3,clk,reset,door,buzzer,
lcd_data,lcd_rs,lcd_en);
//adc I/Os
input [7:0] adc1;
input [7:0] adc2;
input [7:0] adc3;
output adc_wr1;
output adc_wr2;
output adc_wr3;
//LCD I/Os
output [7:0] lcd_data;
output lcd_rs;
output lcd_en;
//Global I/Os
input clk;
input reset;
input door;
output buzzer;
// I/O reg-s
reg buzzer_reg,lcd_rs,lcd_en;
reg [7:0] lcd_data_reg;
reg adc_wr1,adc_wr2,adc_wr3;
//internal Reg-s
reg [16:0] adc_timer;
reg [20:0] lcd_timer;
reg reset_done = 0;
reg [3:0] gas_status;
reg [7:0] char_gas [8:0];
reg [4:0] hum_status;
reg [7:0] hum_char [1:0];
reg [7:0] adc_reg1,adc_reg2,adc_reg3;
reg continue_this_loop;
reg [3:0] yekan ;
reg [3:0] dahgan;
reg [3:0] sadgan;
reg [7:0] bin_temperature;
//----------------------------------
always @(posedge clk or posedge reset)
if (reset)
begin
adc_timer = 0;
lcd_timer = 0;
end
else if (clk)
begin
adc_timer = adc_timer + 1;
lcd_timer = lcd_timer + 1;
end
//-------------------------------------
//in this always-loop we read all adc-s data at once
always @ (adc_timer[16] or adc1 or adc2 or adc3 or reset or door) //
about 13mS /w 10MHz clk
if (reset)
begin
reset_done <= 1;
adc_wr1 <= 1;
adc_wr2 <= 1;
adc_wr3 <= 1;
end
else
begin
adc_wr1 <= 0;
adc_wr2 <= 0;
adc_wr3 <= 0;
adc_reg1 <= adc1;
bin_temperature <= adc_reg1 * 4 ;
adc_reg2 <= adc2;
adc_reg3 <= adc3;
buzzer_reg <= ~ door;
end
//--------------------------------------
always @ ( continue_this_loop or bin_temperature)
begin
if (!reset_done)
begin
yekan=0;
dahgan=0;
sadgan=0;
end
else
begin
if(bin_temperature>8'd100)
begin
sadgan=sadgan+1;
bin_temperature=bin_temperature-100;
continue_this_loop = ~continue_this_loop;
end
else
if(bin_temperature>8'd10)
begin
dahgan=dahgan+1;
bin_temperature=bin_temperature-10;
continue_this_loop = ~continue_this_loop;
end
else
yekan=bin_temperature;
end
end
//--------------------------------------
//humidity read from adc2;
always @ (adc_reg2)
if (adc_reg2>240)
hum_status = 14;
else if (adc_reg2>225)
hum_status = 13;
else if (adc_reg2>210)
hum_status = 12;
else if (adc_reg2>195)
hum_status = 11;
else if (adc_reg2>180)
hum_status = 10;
else if (adc_reg2>165)
hum_status = 9;
else if (adc_reg2>150)
hum_status = 8;
else if (adc_reg2>135)
hum_status = 7;
else if (adc_reg2>120)
hum_status = 6;
else if (adc_reg2>105)
hum_status = 5;
else if (adc_reg2>90)
hum_status = 4;
else if (adc_reg2>75)
hum_status = 3;
else if (adc_reg2>60)
hum_status = 2;
else if (adc_reg2>45)
hum_status = 1;
else if (adc_reg2>30)
hum_status = 0;
// lcd data from humidity sensor.
always @ (hum_status)
case (hum_status)
14:begin
hum_char[0] <= "8" ;
hum_char[1] <= "5" ;
end
13:begin
hum_char[0] <= "8" ;
hum_char[1] <= "0" ;
end
12:begin
hum_char[0] <= "7" ;
hum_char[1] <= "5" ;
end
11:begin
hum_char[0] <= "7" ;
hum_char[1] <= "0" ;
end
10:begin
hum_char[0] <= "6" ;
hum_char[1] <= "5" ;
end
9:begin
hum_char[0] <= "6" ;
hum_char[1] <= "0" ;
end
8:begin
hum_char[0] <= "5" ;
hum_char[1] <= "5" ;
end
7:begin
hum_char[0] <= "5" ;
hum_char[1] <= "0" ;
end
6:begin
hum_char[0] <= "4" ;
hum_char[1] <= "5" ;
end
5:begin
hum_char[0] <= "4" ;
hum_char[1] <= "0" ;
end
4:begin
hum_char[0] <= "3" ;
hum_char[1] <= "5" ;
end
3:begin
hum_char[0] <= "3" ;
hum_char[1] <= "0" ;
end
2:begin
hum_char[0] <= "2" ;
hum_char[1] <= "5" ;
end
1:begin
hum_char[0] <= "2" ;
hum_char[1] <= "0" ;
end
0:begin
hum_char[0] <= "1" ;
hum_char[1] <= "5" ;
end
endcase
//--------------------------------------
always @ (adc_reg3)
if (adc_reg3 >8'd200)
gas_status = 5;
else if (adc_reg3 >8'd150)
gas_status = 4;
else if (adc_reg3 >8'd100)
gas_status = 3;
else if (adc_reg3 >8'd50)
gas_status = 2;
else if (adc_reg3 >8'd0)
gas_status = 1;
always @ (gas_status)
case (gas_status)
1 : begin
char_gas [0] <= "N";
char_gas [1] <= "o";
char_gas [2] <= "r";
char_gas [3] <= "m";
char_gas [4] <= "a";
char_gas [5] <= "l";
char_gas [6] <= " ";
char_gas [7] <= " ";
char_gas [8] <= " ";
end
2 : begin
char_gas [0] <= "L";
char_gas [1] <= "o";
char_gas [2] <= "w";
char_gas [3] <= " ";
char_gas [4] <= " ";
char_gas [5] <= " ";
char_gas [6] <= " ";
char_gas [7] <= " ";
char_gas [8] <= " ";
end
3 : begin
char_gas [0] <= "H";
char_gas [1] <= "i";
char_gas [2] <= "g";
char_gas [3] <= "h";
char_gas [4] <= " ";
char_gas [5] <= " ";
char_gas [6] <= " ";
char_gas [7] <= " ";
char_gas [8] <= " ";
end
4 : begin
char_gas [0] <= "V";
char_gas [1] <= "e";
char_gas [2] <= "r";
char_gas [3] <= "y";
char_gas [4] <= " ";
char_gas [5] <= "H";
char_gas [6] <= "i";
char_gas [7] <= "g";
char_gas [8] <= "h";
end
5 : begin
char_gas [0] <= "D";
char_gas [1] <= "a";
char_gas [2] <= "n";
char_gas [3] <= "g";
char_gas [4] <= "e";
char_gas [5] <= "r";
char_gas [6] <= "o";
char_gas [7] <= "u";
char_gas [8] <= "s";
end
endcase
//--------------------------------------
assign buzzer = buzzer_reg;
assign lcd_data = lcd_data_reg;
//----------------------------------//
// //
// personal comments //
// //
//----------------------------------//
//
//clk input divisions
10MHz/i=?)
// i=2^8 ......... 10 uS
// i=2^15 ......... 3 mS
// i=2^17 ......... 13 mS
// i=2^18 ......... 26 mS
// i=2^19 ......... 52 mS
// i=2^20 ......... 104 mS
// i=2^23 ......... 838 mS
endmodule
i'm a newbe to verilog and fpga.
i'm trying to compile my first group of HDL programs.
but there are lots of trouble-some warnings that made me so tired.
some inputs of the verilog code are not included in the synthesis.
and just 14 out of 41 I/Os are shown in the compile results.
in this code i want to read 3 A/Ds and show their value in 4*20 char-
LCD.
can anybody help me to find out my mistakes
thanks in advance
here are the compile results
//-------------------------------------------------------------------------------------------------------
Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 1.00 s
--> Reading design: freerun.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options
Summary *
=========================================================================
---- Source Parameters
Input File Name : freerun.prj
Input Format : mixed
Ignore Synthesis Constraint File : NO
Verilog Include Directory :
---- Target Parameters
Output File Name : freerun
Output Format : NGC
Target Device : xc9500
---- Source Options
Top Module Name : freerun
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
Equivalent register Removal : YES
MACRO Preserve : YES
XOR Preserve : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
lso : freerun.lso
verilog2001 : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL
Compilation *
=========================================================================
Compiling source file "freerun.v"
Module <freerun> compiled
No errors in compilation
Analysis of file <freerun.prj> succeeded.
=========================================================================
* HDL
Analysis *
=========================================================================
Analyzing top module <freerun>.
WARNING:Xst:905 - freerun.v line 90: The signals <reset_done> are
missing in the sensitivity list of always block.
Module <freerun> is correct for synthesis.
=========================================================================
* HDL
Synthesis *
=========================================================================
Synthesizing Unit <freerun>.
Related source file is freerun.v.
WARNING:Xst:1306 - Output <lcd_en> is never assigned.
WARNING:Xst:1306 - Output <lcd_rs> is never assigned.
WARNING:Xst:646 - Signal <adc_reg1<7:6>> is assigned but never used.
WARNING:Xst:653 - Signal <lcd_data_reg> is used but never assigned.
Tied to value 00000000.
WARNING:Xst:646 - Signal <yekan> is assigned but never used.
WARNING:Xst:646 - Signal <hum_char> is assigned but never used.
WARNING:Xst:646 - Signal <char_gas> is assigned but never used.
WARNING:Xst:737 - Found 1-bit latch for signal <reset_done>.
WARNING:Xst:737 - Found 8-bit latch for signal <adc_reg1>.
WARNING:Xst:737 - Found 8-bit latch for signal <bin_temperature>.
WARNING:Xst:737 - Found 8-bit latch for signal <bin_temperature>.
WARNING:Xst:737 - Found 1-bit latch for signal <buzzer_reg>.
WARNING:Xst:737 - Found 4-bit latch for signal <dahgan>.
WARNING:Xst:737 - Found 4-bit latch for signal <sadgan>.
WARNING:Xst:737 - Found 1-bit latch for signal <continue_this_loop>.
Found 8-bit comparator greater for signal <$n0002> created at line
109.
Found 4-bit adder for signal <$n0004> created at line 111.
Found 8-bit comparator greater for signal <$n0005> created at line
102.
Found 4-bit adder for signal <$n0006> created at line 104.
Found 8-bit subtractor for signal <$n0008>.
Found 17-bit up counter for signal <adc_timer>.
Found 21-bit up counter for signal <lcd_timer>.
Found 9 1-bit 2-to-1 multiplexers.
Summary:
inferred 2 Counter(s).
inferred 3 Adder/Subtracter(s).
inferred 2 Comparator(s).
Unit <freerun> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that
some arithmetic operations in this design can share the same physical
resources for reduced device utilization. For improved clock frequency
you may try to disable resource sharing.
=========================================================================
* Advanced HDL
Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# Latches : 1
1-bit latch : 1
=========================================================================
=========================================================================
* Low Level
Synthesis *
=========================================================================
Optimizing unit <freerun> ...
=========================================================================
* Final
Report *
=========================================================================
Final Results
RTL Top Level Output File Name : freerun.ngr
Top Level Output File Name : freerun
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : xc9500
Macro Preserve : YES
XOR Preserve : YES
wysiwyg : NO
Design Statistics
# IOs : 41
Cell Usage :
# BELS : 3
# GND : 1
# INV : 2
# FlipFlops/Latches : 1
# LD : 1
# IO Buffers : 14
# IBUF : 2
# OBUF : 12
=========================================================================
CPU : 3.59 / 4.78 s | Elapsed : 4.00 / 5.00 s
-->
Total memory usage is 51104 kilobytes
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
//
**********************************************************************************************
// and this is my code
//
**********************************************************************************************
module
freerun(adc1,adc2,adc3,adc_wr1,adc_wr2,adc_wr3,clk,reset,door,buzzer,
lcd_data,lcd_rs,lcd_en);
//adc I/Os
input [7:0] adc1;
input [7:0] adc2;
input [7:0] adc3;
output adc_wr1;
output adc_wr2;
output adc_wr3;
//LCD I/Os
output [7:0] lcd_data;
output lcd_rs;
output lcd_en;
//Global I/Os
input clk;
input reset;
input door;
output buzzer;
// I/O reg-s
reg buzzer_reg,lcd_rs,lcd_en;
reg [7:0] lcd_data_reg;
reg adc_wr1,adc_wr2,adc_wr3;
//internal Reg-s
reg [16:0] adc_timer;
reg [20:0] lcd_timer;
reg reset_done = 0;
reg [3:0] gas_status;
reg [7:0] char_gas [8:0];
reg [4:0] hum_status;
reg [7:0] hum_char [1:0];
reg [7:0] adc_reg1,adc_reg2,adc_reg3;
reg continue_this_loop;
reg [3:0] yekan ;
reg [3:0] dahgan;
reg [3:0] sadgan;
reg [7:0] bin_temperature;
//----------------------------------
always @(posedge clk or posedge reset)
if (reset)
begin
adc_timer = 0;
lcd_timer = 0;
end
else if (clk)
begin
adc_timer = adc_timer + 1;
lcd_timer = lcd_timer + 1;
end
//-------------------------------------
//in this always-loop we read all adc-s data at once
always @ (adc_timer[16] or adc1 or adc2 or adc3 or reset or door) //
about 13mS /w 10MHz clk
if (reset)
begin
reset_done <= 1;
adc_wr1 <= 1;
adc_wr2 <= 1;
adc_wr3 <= 1;
end
else
begin
adc_wr1 <= 0;
adc_wr2 <= 0;
adc_wr3 <= 0;
adc_reg1 <= adc1;
bin_temperature <= adc_reg1 * 4 ;
adc_reg2 <= adc2;
adc_reg3 <= adc3;
buzzer_reg <= ~ door;
end
//--------------------------------------
always @ ( continue_this_loop or bin_temperature)
begin
if (!reset_done)
begin
yekan=0;
dahgan=0;
sadgan=0;
end
else
begin
if(bin_temperature>8'd100)
begin
sadgan=sadgan+1;
bin_temperature=bin_temperature-100;
continue_this_loop = ~continue_this_loop;
end
else
if(bin_temperature>8'd10)
begin
dahgan=dahgan+1;
bin_temperature=bin_temperature-10;
continue_this_loop = ~continue_this_loop;
end
else
yekan=bin_temperature;
end
end
//--------------------------------------
//humidity read from adc2;
always @ (adc_reg2)
if (adc_reg2>240)
hum_status = 14;
else if (adc_reg2>225)
hum_status = 13;
else if (adc_reg2>210)
hum_status = 12;
else if (adc_reg2>195)
hum_status = 11;
else if (adc_reg2>180)
hum_status = 10;
else if (adc_reg2>165)
hum_status = 9;
else if (adc_reg2>150)
hum_status = 8;
else if (adc_reg2>135)
hum_status = 7;
else if (adc_reg2>120)
hum_status = 6;
else if (adc_reg2>105)
hum_status = 5;
else if (adc_reg2>90)
hum_status = 4;
else if (adc_reg2>75)
hum_status = 3;
else if (adc_reg2>60)
hum_status = 2;
else if (adc_reg2>45)
hum_status = 1;
else if (adc_reg2>30)
hum_status = 0;
// lcd data from humidity sensor.
always @ (hum_status)
case (hum_status)
14:begin
hum_char[0] <= "8" ;
hum_char[1] <= "5" ;
end
13:begin
hum_char[0] <= "8" ;
hum_char[1] <= "0" ;
end
12:begin
hum_char[0] <= "7" ;
hum_char[1] <= "5" ;
end
11:begin
hum_char[0] <= "7" ;
hum_char[1] <= "0" ;
end
10:begin
hum_char[0] <= "6" ;
hum_char[1] <= "5" ;
end
9:begin
hum_char[0] <= "6" ;
hum_char[1] <= "0" ;
end
8:begin
hum_char[0] <= "5" ;
hum_char[1] <= "5" ;
end
7:begin
hum_char[0] <= "5" ;
hum_char[1] <= "0" ;
end
6:begin
hum_char[0] <= "4" ;
hum_char[1] <= "5" ;
end
5:begin
hum_char[0] <= "4" ;
hum_char[1] <= "0" ;
end
4:begin
hum_char[0] <= "3" ;
hum_char[1] <= "5" ;
end
3:begin
hum_char[0] <= "3" ;
hum_char[1] <= "0" ;
end
2:begin
hum_char[0] <= "2" ;
hum_char[1] <= "5" ;
end
1:begin
hum_char[0] <= "2" ;
hum_char[1] <= "0" ;
end
0:begin
hum_char[0] <= "1" ;
hum_char[1] <= "5" ;
end
endcase
//--------------------------------------
always @ (adc_reg3)
if (adc_reg3 >8'd200)
gas_status = 5;
else if (adc_reg3 >8'd150)
gas_status = 4;
else if (adc_reg3 >8'd100)
gas_status = 3;
else if (adc_reg3 >8'd50)
gas_status = 2;
else if (adc_reg3 >8'd0)
gas_status = 1;
always @ (gas_status)
case (gas_status)
1 : begin
char_gas [0] <= "N";
char_gas [1] <= "o";
char_gas [2] <= "r";
char_gas [3] <= "m";
char_gas [4] <= "a";
char_gas [5] <= "l";
char_gas [6] <= " ";
char_gas [7] <= " ";
char_gas [8] <= " ";
end
2 : begin
char_gas [0] <= "L";
char_gas [1] <= "o";
char_gas [2] <= "w";
char_gas [3] <= " ";
char_gas [4] <= " ";
char_gas [5] <= " ";
char_gas [6] <= " ";
char_gas [7] <= " ";
char_gas [8] <= " ";
end
3 : begin
char_gas [0] <= "H";
char_gas [1] <= "i";
char_gas [2] <= "g";
char_gas [3] <= "h";
char_gas [4] <= " ";
char_gas [5] <= " ";
char_gas [6] <= " ";
char_gas [7] <= " ";
char_gas [8] <= " ";
end
4 : begin
char_gas [0] <= "V";
char_gas [1] <= "e";
char_gas [2] <= "r";
char_gas [3] <= "y";
char_gas [4] <= " ";
char_gas [5] <= "H";
char_gas [6] <= "i";
char_gas [7] <= "g";
char_gas [8] <= "h";
end
5 : begin
char_gas [0] <= "D";
char_gas [1] <= "a";
char_gas [2] <= "n";
char_gas [3] <= "g";
char_gas [4] <= "e";
char_gas [5] <= "r";
char_gas [6] <= "o";
char_gas [7] <= "u";
char_gas [8] <= "s";
end
endcase
//--------------------------------------
assign buzzer = buzzer_reg;
assign lcd_data = lcd_data_reg;
//----------------------------------//
// //
// personal comments //
// //
//----------------------------------//
//
//clk input divisions
10MHz/i=?)// i=2^8 ......... 10 uS
// i=2^15 ......... 3 mS
// i=2^17 ......... 13 mS
// i=2^18 ......... 26 mS
// i=2^19 ......... 52 mS
// i=2^20 ......... 104 mS
// i=2^23 ......... 838 mS
endmodule