XST & Verilog constraint name with genvar variable

[nachumk]

How do I create a concatenated string that for constraints using XST
and Verilog? Basically I want to be able to create U_SET constraints
within a generated block with names that are counted by using the
genvar variable. This is important if I want to separate using U_SETs
both the generate iterations and additional generate loops later in
the code. For example:

genvar g;
generate
for(g = 0; g < 8; g = g + 1) begin : a_gen
(* U_SET = {"a",g} *)
(* RLOC = X0Y0 *)
//dsp 0 inst
(* RLOC = X0Y1 *)
//dsp 1 inst
end
for(g = 0; g < 8; g = g + 1) begin : b_gen
(* U_SET = {"b",g} *)
(* RLOC = X0Y0 *)
//dsp 0 inst
(* RLOC = X0Y1 *)
//dsp 1 inst
end
endgenerate

XST doesn't accept any constraint name other than either a direct
string or just the genvar variable. I need to give it a string +
genvar variable.

Any help would be appreciated,

Thanx
Nachum Kanovsky

PS - This was posted incorrectly to comp.arch.fpga earlier - I have it
removed it from there.

 

[Muzaffer Kal]

On Thu, 6 Aug 2009 15:55:17 -0700 (PDT), sharp@cadence.com wrote:

On Aug 6, 5:22 am, nachumk <nach...@gmail.com> wrote:
How do I create a concatenated string that for constraints using XST
and Verilog?

XST doesn't accept any constraint name other than either a direct
string or just the genvar variable. I need to give it a string +
genvar variable.

In theory, you can set an attribute to any constant expression. In
practice, you are limited to what the tool supports.

You might try declaring a parameter or localparam inside the generate,
setting that to your desired value, and then using that in the
attribute:

for (g = 0; g < 8; g = g + 1) begin: a_gen
localparam u_set = {"a",g};
(* U_SET = u_set *)

Even if this works, I doubt it will behave the way you want. The
result of {"a",g} when g is 0 is not "a0". It is a 5-byte vector with
"a" followed by 4 bytes of ASCII NUL characters (bytes with value 0).
The number 0 and the ASCII character "0" are not the same thing at
all.

Then how about

localparam [7:0] gb = g+8'h40;
localparam u_set = {'a', gb, 8'h0};

Being able to pass constructed strings to attributes is one of the
cases where VHDL is stronger. I am not sure if any Verilog synthesis
tool is flexible enough to understand the intent of the construct
above.

-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

On Aug 6, 5:22 am, nachumk <nach...@gmail.com> wrote:

How do I create a concatenated string that for constraints using XST
and Verilog?

XST doesn't accept any constraint name other than either a direct
string or just the genvar variable. I need to give it a string +
genvar variable.

In theory, you can set an attribute to any constant expression. In
practice, you are limited to what the tool supports.

You might try declaring a parameter or localparam inside the generate,
setting that to your desired value, and then using that in the
attribute:

for (g = 0; g < 8; g = g + 1) begin: a_gen
localparam u_set = {"a",g};
(* U_SET = u_set *)

Even if this works, I doubt it will behave the way you want. The
result of {"a",g} when g is 0 is not "a0". It is a 5-byte vector with
"a" followed by 4 bytes of ASCII NUL characters (bytes with value 0).
The number 0 and the ASCII character "0" are not the same thing at
all.

 

[nachumk]

On Aug 7, 2:27 am, Muzaffer Kal <k...@dspia.com> wrote:

On Thu, 6 Aug 2009 15:55:17 -0700 (PDT), sh...@cadence.com wrote:
On Aug 6, 5:22 am, nachumk <nach...@gmail.com> wrote:
How do I create a concatenated string that for constraints using XST
and Verilog?

XST doesn't accept any constraint name other than either a direct
string or just the genvar variable. I need to give it a string +
genvar variable.

In theory, you can set an attribute to any constant expression.  In
practice, you are limited to what the tool supports.

You might try declaring a parameter or localparam inside the generate,
setting that to your desired value, and then using that in the
attribute:

for (g = 0; g < 8; g = g + 1) begin: a_gen
 localparam u_set = {"a",g};
 (* U_SET = u_set *)

Even if this works, I doubt it will behave the way you want.  The
result of {"a",g} when g is 0 is not "a0".  It is a 5-byte vector with
"a" followed by 4 bytes of ASCII NUL characters (bytes with value 0).
The number 0 and the ASCII character "0" are not the same thing at
all.

Then how about

localparam [7:0] gb = g+8'h40;
localparam u_set = {'a', gb, 8'h0};

Being able to pass constructed strings to attributes is one of the
cases where VHDL is stronger.  I am not sure if any Verilog synthesis
tool is flexible enough to  understand the intent of the construct
above.

-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Sadly localparam is not legal within a generate block...

 

On Aug 6, 7:27 pm, Muzaffer Kal <k...@dspia.com> wrote:

Then how about

localparam [7:0] gb = g+8'h40;
localparam u_set = {'a', gb, 8'h0};

No need for a null byte at the end, as this is not a C null-terminated
string. In theory, you should be able to do this with

localparam u_set = {"a", g[7:0] + "0"};

 

On Aug 7, 7:48 am, nachumk <nach...@gmail.com> wrote:

Sadly localparam is not legal within a generate block...

This omission was fixed in the 2005 standard. But you are still
limited to what your tools implement.

I see an ugly workaround for this, by replacing the localparam with a
genvar in a nested loop that only executes once:

for (g = 0; g < 8; g = g + 1) begin : a_gen
genvar u_set;
for (u_set = {"a", g[7:0] + "0"}; u_set; u_set = 0) begin : dummy
(* U_SET = u_set *)

If your tools don't support a part-select of a genvar, or something
else in the expression, you can build the same thing with

u_set = "a0" + g