XST - timing constraints of the combinatorial logic

L

lyo34

Guest
Hello,

I am dealing with some issues with timing
delays.I would like to know how to implement
timing constraints for combinatorial nets
in a simple way.

For example:
an AND gate with two inputs: A and B
and I want to force XST to guarantee that
the signal A arrives before B. I precise that
the AND gate is one element of a combinatorial
path (A and B are not PADs).

Any ideas?

Thanks for your help.




---------------------------------------
Posted through http://www.FPGARelated.com
 
Why exactly do you want to do this?

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Apr 16, 7:38 am, "lyo34" <lyonel.barthe@n_o_s_p_a_m.lirmm.fr>
wrote:
Hello,

I am dealing with some issues with timing
delays.I would like to know how to implement
timing constraints for combinatorial nets
in a simple way.

For example:
an AND gate with two inputs: A and B
and I want to force XST to guarantee that
the signal A arrives before B. I precise that
the AND gate is one element of a combinatorial
path (A and B are not PADs).

Any ideas?

Thanks for your help.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
A synthesizer (XST in your case) cannot guarantee any timing it can
only provide estimates. The only way to determine if the timing is
identical would be after the entire path has been placed and routed.

And then due to process variation with any IC the delays will never be
identical.

Ed McGettigan
--
Xilinx Inc.
 
On Apr 16, 7:38=A0am, "lyo34" <lyonel.barthe@n_o_s_p_a_m.lirmm.fr
wrote:
Hello,

I am dealing with some issues with timing
delays.I would like to know how to implement
timing constraints for combinatorial nets
in a simple way.

For example:
an AND gate with two inputs: A and B
and I want to force XST to guarantee that
the signal A arrives before B. I precise that
the AND gate is one element of a combinatorial
path (A and B are not PADs).

Any ideas?

Thanks for your help.

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

A synthesizer (XST in your case) cannot guarantee any timing it can
only provide estimates. The only way to determine if the timing is
identical would be after the entire path has been placed and routed.

And then due to process variation with any IC the delays will never be
identical.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Thanks for your answer.

I was hoping there was a clever way
to do that... like the hold violations
which are managed by the synthesizer
with extra buffers.





---------------------------------------
Posted through http://www.FPGARelated.com
 
On Apr 23, 12:09 am, "lyo34"
<lyonel.barthe@n_o_s_p_a_m.n_o_s_p_a_m.lirmm.fr> wrote:
On Apr 16, 7:38=A0am, "lyo34" <lyonel.barthe@n_o_s_p_a_m.lirmm.fr
wrote:
Hello,

I am dealing with some issues with timing
delays.I would like to know how to implement
timing constraints for combinatorial nets
in a simple way.

For example:
an AND gate with two inputs: A and B
and I want to force XST to guarantee that
the signal A arrives before B. I precise that
the AND gate is one element of a combinatorial
path (A and B are not PADs).

Any ideas?

Thanks for your help.

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

A synthesizer (XST in your case) cannot guarantee any timing it can
only provide estimates.  The only way to determine if the timing is
identical would be after the entire path has been placed and routed.

And then due to process variation with any IC the delays will never be
identical.

Ed McGettigan
--
Xilinx Inc.

Thanks for your answer.

I was hoping there was a clever way
to do that... like the hold violations
which are managed by the synthesizer
with extra buffers.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
I am not sure if Xilinx fixed hold violations but vaguely remember it
might have shown me hold violations. I am not really sure. But there
should be a way to get the delay between flops where you know that the
path is failing on hold. Ideally Xilinx flops should not fail on hold
since the clock skew is much smaller. May be places where local
routing for clocks are used and if the skew is more, these violations
might happen. Either way the Xilinx Timing analyzer puts up a lot of
information as far as timing is concerned and things can be fixed.
Personally, I don't think Xilinx FPGAs fail on hold for internal flip
flops. The pads story might be different.

Thanks
Shyam
 
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