XST (ISE 6.1i): Error: It's interesting and surprising

[QRaheeL]

Hi guys.

An intesresting problem occured when I used "more than three" signals
in always block sens list.

XST (ISE 6.1i) reported the following error:

ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block
sensitivity list.

Same code is successfully compiled & simulated in MOdelSim5.7SE.

What kind of problem is this ?
Related to parser/editor/etc ??

//-------- C O D E - C O D E --------///

module dummy(x);
output x;
assign x = 1'b0;

reg a,b,c,d;
reg z;

initial
begin
a=0; b=0; c=0; d=0; z=0;
#100 $stop;
end

always #10 a=~a;
always #15 b=~b;
always #20 c=~c;
always #5 d=~d;

always @(posedge a or posedge b or posedge c or posedge d ) begin
if(a) z=~z;
else if(b)z=~z;
else if(c) z=~z;
else if(d) z=~z;
end
endmodule

 

[Marko]

Most of your code can be simulated but not synthesized.

Ask yourself what hardware can XST use to create signals a,b,c and d.


On 14 Aug 2005 12:28:23 -0700, "QRaheeL" <qraheel@gmail.com> wrote:

Hi guys.

An intesresting problem occured when I used "more than three" signals
in always block sens list.

XST (ISE 6.1i) reported the following error:

ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block
sensitivity list.

Same code is successfully compiled & simulated in MOdelSim5.7SE.

What kind of problem is this ?
Related to parser/editor/etc ??

//-------- C O D E - C O D E --------///

module dummy(x);
output x;
assign x = 1'b0;

reg a,b,c,d;
reg z;

initial
begin
a=0; b=0; c=0; d=0; z=0;
#100 $stop;
end

always #10 a=~a;
always #15 b=~b;
always #20 c=~c;
always #5 d=~d;

always @(posedge a or posedge b or posedge c or posedge d ) begin
if(a) z=~z;
else if(b)z=~z;
else if(c) z=~z;
else if(d) z=~z;
end
endmodule

 

[Rob Dekker]

"QRaheeL" <qraheel@gmail.com> wrote in message news:1124047703.429579.249220@g43g2000cwa.googlegroups.com...

Hi guys.

An intesresting problem occured when I used "more than three" signals
in always block sens list.

XST (ISE 6.1i) reported the following error:

ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block
sensitivity list.

Same code is successfully compiled & simulated in MOdelSim5.7SE.

The message is pretty bad, but there is a synthesis issue here.
Many other synthesis / verification tools give messages similar to this :

senselist.v(1): INFO: compiling module dummy (VERI-1018)
senselist.v(12): WARNING: 'initial' construct ignored (VERI-1060)
senselist.v(20): WARNING: z should be on the sensitivity list (VERI-1221)
senselist.v(21): WARNING: z should be on the sensitivity list (VERI-1221)
senselist.v(22): WARNING: z should be on the sensitivity list (VERI-1221)

That is more helpfull, since you are toggling a signal under an asynchronous condition.

always @(posedge a or posedge b or posedge c or posedge d ) begin
if(a) z=~z; // line 20
else if(b)z=~z;
else if(c) z=~z;
else if(d) z=~z;
....

The question is : What kind of hardware are you trying to synthesize ?

 

[Andy Peters]

QRaheeL wrote:

An intesresting problem occured when I used "more than three" signals
in always block sens list.

XST (ISE 6.1i) reported the following error:

ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block
sensitivity list.

Same code is successfully compiled & simulated in MOdelSim5.7SE.

What kind of problem is this ?
Related to parser/editor/etc ??

//-------- C O D E - C O D E --------///

module dummy(x);
output x;
assign x = 1'b0;

reg a,b,c,d;
reg z;

initial
begin
a=0; b=0; c=0; d=0; z=0;
#100 $stop;
end

always #10 a=~a;
always #15 b=~b;
always #20 c=~c;
always #5 d=~d;

always @(posedge a or posedge b or posedge c or posedge d ) begin
if(a) z=~z;
else if(b)z=~z;
else if(c) z=~z;
else if(d) z=~z;
end
endmodule

Are you trying to synthesize this, or is it part of a testbench? I
suspect it's the latter.

Oh, by the way, you shouldn't use initial blocks to initialize
variables. There's no guarantee that the initial block will be called
before the always block. initial blocks are just like always blocks,
except they run once.

-a

 

[Art Stamness]

Actually in his case the Initial blocks are called before the always.
Notice after each always keyword, there is a # delay. This is a pretty
standard way of writing a clock generator :

reg clk ;
initial clk = 1'b0 ;
always #5 clk = ~clk ;

I however have nothing good to say about the later always @( posedge a
.... posedge d ). Since startup value for reg z is 1'bx, and since
~(1'bx) is just (1'bx), reg z, never really does anything, but stay
1'bx.

Now if this were initialized then you have a whole other mess of code
here. Because if math serves me correct 5,10,15, and 25 will align many
times. And each time you have multiple evaluations of your posedge
block. This means that in the worst case scenario at time #300, when
all of these are firing, z could transition 0 -> 1 ->0 -> 1-> 0, in the
same time slice. Now if for some awful reason z is used as a clock
input ( like for always @(posege z) ) , you are going to have som
really really awful behavior.

And then depending on the format you dump in, you might not be even
able to see those transitions unless features like glitch detection are
enabled.

Summary : This is bad bad code.


-Art