A
Allan Herriman
Guest
Hi,
I'm trying to code this structure in Verilog. There are two flip
flops (c and d) that are identical. XST 6.1.3 wants to merge them
together. I want to stop it from doing that.
e .---. c
+-----|D Q|-----
| +-|>C |
a .---. b | | | |
----|D Q|-----+ | '---'
+--|>C | | |
| | | | |
| '---' | f | .---. d
| +-----|D Q|-----
clk-+----------------+-|>C |
| |
'---'
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
I am giving the -equivalent_register_removal YES option to XST (it's
needed elsewhere in the design) so I have to use attributes to stop
XST from merging these particular ffs, since I don't wish to
instantiate unisim components.
When I use the keep attribute on all of c, d, e and f, XST still
merges the ffs, and comes back with this warning:
WARNING:Xst:638 - in unit foo Conflict on KEEP property on signal e
and f f signal will be lost.
[ Warning 638 isn't in the Xilinx documentation or the answers
database. ]
Here's the Verilog:
module foo
(
input wire clk,
input wire a,
output reg c,
output reg d
);
reg b;
wire e = b;
wire f = b;
// synthesis attribute keep of c is "true"
// synthesis attribute keep of d is "true"
// synthesis attribute keep of e is "true"
// synthesis attribute keep of f is "true"
always @(posedge clk)
begin
b <= a;
c <= e;
d <= f;
end
endmodule
I have a working solution: add BUFs as follows:
BUF buf_e (.I(b), .O(e));
BUF buf_f (.I(b), .O(f));
This produces the correct result after synthesis, but I wish to avoid
using unisim components, because (1) they slow my simulation (even BUF
contains a specify block!), (2) they aren't portable, and (3) I
shouldn't have to.
Questions:
- What am I doing wrong? ("Expecting too much from XST" is not an
acceptable answer.)
- How can I write the Verilog such that I get the correct result after
synthesis without needing to instantiate unisim components?
Hint to Xilinx: a "preserve" attribute would be really handy. The
other synthesis vendors have it. Why doesn't XST?
Thanks,
Allan.
I'm trying to code this structure in Verilog. There are two flip
flops (c and d) that are identical. XST 6.1.3 wants to merge them
together. I want to stop it from doing that.
e .---. c
+-----|D Q|-----
| +-|>C |
a .---. b | | | |
----|D Q|-----+ | '---'
+--|>C | | |
| | | | |
| '---' | f | .---. d
| +-----|D Q|-----
clk-+----------------+-|>C |
| |
'---'
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
I am giving the -equivalent_register_removal YES option to XST (it's
needed elsewhere in the design) so I have to use attributes to stop
XST from merging these particular ffs, since I don't wish to
instantiate unisim components.
When I use the keep attribute on all of c, d, e and f, XST still
merges the ffs, and comes back with this warning:
WARNING:Xst:638 - in unit foo Conflict on KEEP property on signal e
and f f signal will be lost.
[ Warning 638 isn't in the Xilinx documentation or the answers
database. ]
Here's the Verilog:
module foo
(
input wire clk,
input wire a,
output reg c,
output reg d
);
reg b;
wire e = b;
wire f = b;
// synthesis attribute keep of c is "true"
// synthesis attribute keep of d is "true"
// synthesis attribute keep of e is "true"
// synthesis attribute keep of f is "true"
always @(posedge clk)
begin
b <= a;
c <= e;
d <= f;
end
endmodule
I have a working solution: add BUFs as follows:
BUF buf_e (.I(b), .O(e));
BUF buf_f (.I(b), .O(f));
This produces the correct result after synthesis, but I wish to avoid
using unisim components, because (1) they slow my simulation (even BUF
contains a specify block!), (2) they aren't portable, and (3) I
shouldn't have to.
Questions:
- What am I doing wrong? ("Expecting too much from XST" is not an
acceptable answer.)
- How can I write the Verilog such that I get the correct result after
synthesis without needing to instantiate unisim components?
Hint to Xilinx: a "preserve" attribute would be really handy. The
other synthesis vendors have it. Why doesn't XST?
Thanks,
Allan.