C
cfelton
Guest
XST Fails 2D array wild card sensitivity list
XST fails the following Verilog (similar HDL) where other synthesizers
compilers do not?
wire [15:0] x [0:15];
wire [15:0] y [0:15];
wire [15:0] z;
wire [15:0] xo [0:15];
wire [15:0] yo [0:15];
always @(*) begin
if (cnt < 8) begin
xo[cnt] = x[cnt];
yo[cnt] = y[cnt];
end
else begin
xo[cnt] = z;
yo[cnt] = 16âb0;
end
end
HDL similar to the above fails in XST but synthesizes / compiles correctl
in all of the following
Icarus Verilog
Modelsim
Ncsim
Cadence RTL Compiler
Synplify Pro
Altera Quartus
Does XST simply not support this?
Or is the above not defined by the Verilog 1364 and the others just suppor
it anyway? Or is there an XST switch that I am missing?
.chris
---------------------------------------
Posted through http://www.FPGARelated.com
XST fails the following Verilog (similar HDL) where other synthesizers
compilers do not?
wire [15:0] x [0:15];
wire [15:0] y [0:15];
wire [15:0] z;
wire [15:0] xo [0:15];
wire [15:0] yo [0:15];
always @(*) begin
if (cnt < 8) begin
xo[cnt] = x[cnt];
yo[cnt] = y[cnt];
end
else begin
xo[cnt] = z;
yo[cnt] = 16âb0;
end
end
HDL similar to the above fails in XST but synthesizes / compiles correctl
in all of the following
Icarus Verilog
Modelsim
Ncsim
Cadence RTL Compiler
Synplify Pro
Altera Quartus
Does XST simply not support this?
Or is the above not defined by the Verilog 1364 and the others just suppor
it anyway? Or is there an XST switch that I am missing?
.chris
---------------------------------------
Posted through http://www.FPGARelated.com