XST - configuration - VHDL

  • Thread starter Jaime Andrés Aranguren Ca
  • Start date
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Jaime Andrés Aranguren Ca

Guest
Dear all,

In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:

-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);

Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:

process_out : process (in_a, in_b)
variable var : std_logic_vector (KA-KB-1 downto 0) := (others =>
'0');
begin

I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:

Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.

But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.

I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.

How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?

Thanks a lot in advance,

JaaC
 
On Nov 10, 10:53 am, Jaime Andrés Aranguren Cardona
<jaime.arangu...@gmail.com> wrote:
Dear all,

In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:

-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);

Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:

process_out : process (in_a, in_b)
    variable var : std_logic_vector (KA-KB-1 downto 0)  := (others =
'0');
  begin

I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:

Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.

But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.

I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.

How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?

Thanks a lot in advance,

JaaC
Click to expand...
Unlike simulation tools, synthesis tools combine the analysis and
elaboration phases into one. This is probably leading to your problem.
Leaving something out in a configuration is not quite like
conditionally compiling it. Everything gets analyzed (if it is in a
file that is being analyzed), whether it is chosen at elaboration or
not. Some simulators have options for compiling (analyzing) only
certain types of units (packages, package bodies, entities,
architectures, etc.) and ignoring others in the same file. I have not
seen that in a synthesis tool.

Other than fixing the problem with the mismatched size (if even
possible), I would suggest moving the two architectures into separate
files, and only including the appropriate file in the project.

Andy
 
On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote:
On Nov 10, 10:53 am, Jaime Andrés Aranguren Cardona



jaime.arangu...@gmail.com> wrote:
Dear all,

In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:

-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);

Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:

process_out : process (in_a, in_b)
    variable var : std_logic_vector (KA-KB-1 downto 0)  := (others =
'0');
  begin

I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:

Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.

But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.

I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.

How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?

Thanks a lot in advance,

JaaC

Unlike simulation tools, synthesis tools combine the analysis and
elaboration phases into one. This is probably leading to your problem.
Leaving something out in a configuration is not quite like
conditionally compiling it. Everything gets analyzed (if it is in a
file that is being analyzed), whether it is chosen at elaboration or
not. Some simulators have options for compiling (analyzing) only
certain types of units (packages, package bodies, entities,
architectures, etc.) and ignoring others in the same file. I have not
seen that in a synthesis tool.

Other than fixing the problem with the mismatched size (if even
possible), I would suggest moving the two architectures into separate
files, and only including the appropriate file in the project.

Andy
Click to expand...
Hi Andy,

Thanks for your reply, I found the solution however: adding pragmas:

architecture struct of Stack2D is

signal dat_2ext : buf2dwrd;
signal rd_2ext : std_logic;
signal dat_2slv : buf2dwrd;
signal wr_2slv : std_logic;

-- pragma synthesis on
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
-- pragma synthesis off

begin

The commented pragmas did the job.

Regards.
 
On 10 Nov., 19:50, Jaime Andrés Aranguren Cardona
<jaime.arangu...@gmail.com> wrote:
On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote:



On Nov 10, 10:53 am, Jaime Andrés Aranguren Cardona

jaime.arangu...@gmail.com> wrote:
Dear all,

In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:

-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);

Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:

process_out : process (in_a, in_b)
    variable var : std_logic_vector (KA-KB-1 downto 0)  := (others =
'0');
  begin

I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:

Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.

But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.

I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.

How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?

Thanks a lot in advance,

JaaC

Unlike simulation tools, synthesis tools combine the analysis and
elaboration phases into one. This is probably leading to your problem.
Leaving something out in a configuration is not quite like
conditionally compiling it. Everything gets analyzed (if it is in a
file that is being analyzed), whether it is chosen at elaboration or
not. Some simulators have options for compiling (analyzing) only
certain types of units (packages, package bodies, entities,
architectures, etc.) and ignoring others in the same file. I have not
seen that in a synthesis tool.

Other than fixing the problem with the mismatched size (if even
possible), I would suggest moving the two architectures into separate
files, and only including the appropriate file in the project.

Andy

Hi Andy,

Thanks for your reply, I found the solution however: adding pragmas:

architecture struct of Stack2D is

  signal dat_2ext : buf2dwrd;
  signal rd_2ext  : std_logic;
  signal dat_2slv : buf2dwrd;
  signal wr_2slv  : std_logic;

  -- pragma synthesis on
  for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
  -- pragma synthesis off

begin

The commented pragmas did the job.

Regards.
Click to expand...
Dear all,

By the way, is there a way to make a conditional selection of
architecture to use, something in the lines of:

for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a) else
use entity work.Ctrl2D(architecture_b); ???

Or is there an alternative approach?

Thanks lot in advance.

JaaC
 
On 11/10/2010 10:54 AM, Jaime Andrés Aranguren Cardona wrote:


architecture struct of Stack2D is

signal dat_2ext : buf2dwrd;
signal rd_2ext : std_logic;
signal dat_2slv : buf2dwrd;
signal wr_2slv : std_logic;

-- pragma synthesis on
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
-- pragma synthesis off

begin

The commented pragmas did the job.
Click to expand...
Maybe.
Were both architectures in the synthesis file list?
If so which one was first?

I use a similar trick to insert debug code into synthesis sources:

-- synthesis translate off
spy: process (strobe_s) is
begin -- process watch
if falling_edge(strobe_s) then
report("data = ", work.my_pkg.std2hexstr(my_ctr));
end if;
end process spy;
-- synthesis translate on


By the way, is there a way to make a conditional selection of
architecture to use, something in the lines of:

for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a) else
use entity work.Ctrl2D(architecture_b); ???
Click to expand...
Not that I know of for synthesis, where I must declare
one top entity and file list. There is no notion
of vhdl libraries or configurations.

Or is there an alternative approach?
Click to expand...
I could generate one direct instance or another
based on a packaged constant value, but I find this confusing.

If the architecture differences are much less the spare fpga resources,
I might combine both modes and select using a mode
register or a jumper.

-- Mike Treseler
 
On Nov 10, 12:54 pm, Jaime Andrés Aranguren Cardona
<jaime.arangu...@gmail.com> wrote:
On 10 Nov., 19:50, Jaime Andrés Aranguren Cardona





jaime.arangu...@gmail.com> wrote:
On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote:

On Nov 10, 10:53 am, Jaime Andrés Aranguren Cardona

jaime.arangu...@gmail.com> wrote:
Dear all,

In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:

-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);

Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:

process_out : process (in_a, in_b)
    variable var : std_logic_vector (KA-KB-1 downto 0)  := (others =
'0');
  begin

I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:

Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.

But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.

I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.

How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?

Thanks a lot in advance,

JaaC

Unlike simulation tools, synthesis tools combine the analysis and
elaboration phases into one. This is probably leading to your problem..
Leaving something out in a configuration is not quite like
conditionally compiling it. Everything gets analyzed (if it is in a
file that is being analyzed), whether it is chosen at elaboration or
not. Some simulators have options for compiling (analyzing) only
certain types of units (packages, package bodies, entities,
architectures, etc.) and ignoring others in the same file. I have not
seen that in a synthesis tool.

Other than fixing the problem with the mismatched size (if even
possible), I would suggest moving the two architectures into separate
files, and only including the appropriate file in the project.

Andy

Hi Andy,

Thanks for your reply, I found the solution however: adding pragmas:

architecture struct of Stack2D is

  signal dat_2ext : buf2dwrd;
  signal rd_2ext  : std_logic;
  signal dat_2slv : buf2dwrd;
  signal wr_2slv  : std_logic;

  -- pragma synthesis on
  for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
  -- pragma synthesis off

begin

The commented pragmas did the job.

Regards.

Dear all,

By the way, is there a way to make a conditional selection of
architecture to use, something in the lines of:

for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a)  else
use entity work.Ctrl2D(architecture_b);   ???

Or is there an alternative approach?

Thanks lot in advance.

JaaC- Hide quoted text -

- Show quoted text -
Click to expand...
The only way to do that is with an if-generate on the instantiation,
not the configuration.

In fact, since the '93 standard, you can directly instantiate an
entity and its architecture:

if a = 0 generate
u1: entity work.entity_name(architecture_name)...
end generate;

if a /= 0 generate
u1: entity work.entity_name(alternative_architecture_name) ...
end generate;

You don't even need to mess with a configuration!

Andy
 
On 11 Nov., 18:03, Andy <jonesa...@comcast.net> wrote:
On Nov 10, 12:54 pm, Jaime Andrés Aranguren Cardona





jaime.arangu...@gmail.com> wrote:
On 10 Nov., 19:50, Jaime Andrés Aranguren Cardona

jaime.arangu...@gmail.com> wrote:
On 10 Nov., 19:16, Andy <jonesa...@comcast.net> wrote:

On Nov 10, 10:53 am, Jaime Andrés Aranguren Cardona

jaime.arangu...@gmail.com> wrote:
Dear all,

In my current project I have an entity for which I which arhitecture
to use on a VHDL file where I instantiate the entity, like following
configuration code:

-- Embedded configuration
-- Select control architecture to use
for all : Ctrl2D use entity work.Ctrl2D(rtl_small);

Within the VHDL file where Ctrl2D is defined, I have different
configurations, namely rtl_tiny and rtl_small. Within each of those,
are processes which have variables whose length depend on some
constants (KA, KB), like:

process_out : process (in_a, in_b)
    variable var : std_logic_vector (KA-KB-1 downto 0)  := (others =
'0');
  begin

I should select which architecture to use in the configuration
(rtl_tiny or rtl_small) depending on a given a given set of values KA
and KB. For a set of values KA and KB that works fine with rtl_small
and having rtl_small selected in the configuration, XST, when parsing,
gives me warnign and error messages:

Entity <Ctrl2D> compiled.
WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null
range: -33 downto 0
ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of
concat operation is different than size of the target.
Entity <Ctrl2D> (Architecture <rtl_small>) compiled.

But those lines (157 and 214) are within the architecture rtl_tiny,
not rtl_small.

I was confident that by selecting the right architecture in the
configuration I was completely bypassing everything related to non-
desired architectures, but it seems like I was wrong.

How can I direct XST to ignore the code of the non-interesting
architectures, and parse and synthesize only the one that I selected
in the configuration?

Thanks a lot in advance,

JaaC

Unlike simulation tools, synthesis tools combine the analysis and
elaboration phases into one. This is probably leading to your problem.
Leaving something out in a configuration is not quite like
conditionally compiling it. Everything gets analyzed (if it is in a
file that is being analyzed), whether it is chosen at elaboration or
not. Some simulators have options for compiling (analyzing) only
certain types of units (packages, package bodies, entities,
architectures, etc.) and ignoring others in the same file. I have not
seen that in a synthesis tool.

Other than fixing the problem with the mismatched size (if even
possible), I would suggest moving the two architectures into separate
files, and only including the appropriate file in the project.

Andy

Hi Andy,

Thanks for your reply, I found the solution however: adding pragmas:

architecture struct of Stack2D is

  signal dat_2ext : buf2dwrd;
  signal rd_2ext  : std_logic;
  signal dat_2slv : buf2dwrd;
  signal wr_2slv  : std_logic;

  -- pragma synthesis on
  for all : Ctrl2D use entity work.Ctrl2D(rtl_small);
  -- pragma synthesis off

begin

The commented pragmas did the job.

Regards.

Dear all,

By the way, is there a way to make a conditional selection of
architecture to use, something in the lines of:

for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a)  else
use entity work.Ctrl2D(architecture_b);   ???

Or is there an alternative approach?

Thanks lot in advance.

JaaC- Hide quoted text -

- Show quoted text -

The only way to do that is with an if-generate on the instantiation,
not the configuration.

In fact, since the '93 standard, you can directly instantiate an
entity and its architecture:

if a = 0 generate
u1: entity work.entity_name(architecture_name)...
end generate;

if a /= 0 generate
u1: entity work.entity_name(alternative_architecture_name) ...
end generate;

You don't even need to mess with a configuration!

Andy- Zitierten Text ausblenden -

- Zitierten Text anzeigen -
Click to expand...
Dear all,

Thanks for the feedback. Andy's suggestion seems to be very in the
direction I was heading for, thanks a lot.

Kindest regards,

JaaC
 
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