xst: assign

J

Jan Bruns

Guest
Hallo,

First, a working example:

module testrom1 (a,o);
input a;
output o;
reg o;
always @(a) begin
o = a;
end
endmodule

While the following 2 prodcuce errors:

module testrom2 (a,o);
input a;
output o;
reg o;
always @(a) assign o = a;
endmodule
-> ERROR:Xst:855 - Unsupported procedural assignment for signal <o>.

module testrom3 (a,o);
input a;
output o;
always @(a) assign o = a;
endmodule
ERROR:HDLCompilers:42 - testrom.v line 4 Illegal LHS of procedural continuous assignment
Click to expand...

Te me, this looked like xst doesn't like assignment to nets.

But, in contrast, look at this possibly working example:

module testmul(q, a,b, clk);
output [31:0] q;
reg [31:0] q;
input [15:0] a,b;
input clk;
always @(posedge clk)
begin
q = a*b;
assign q = q; //coment this, and the pad won't get result
end
endmodule

With "assign q = q;" commented out, timingan can't detect"a<0>(Pad) to q<31>(Pad)"-Path.
What's the reason for this?

Gruss

Jan Bruns
 
"John_H":
The always block doesn't allow the "assign" keyword. It's for use outside
the always blocks. Your "pssibly working example" shouldn't compile if the
assign is in the always block.
Click to expand...
Hm, xst seems at least to allow assign outside of always-blocks.

On the other hand, the XST User Guide states:

| The assign / deassign statement must be performed in the
| same always block through an if /else statement.

and all of the 4 assign examples (3 of them are declared as non-workung
don't do this examples) in that book use assign within always-blocks.

I've modified my testmul-example to:

module testmul(q, a,b, clk);
output [31:0] q;
reg [31:0] q2;
input [15:0] a,b;
input clk;
assign q = q2;
always @(posedge clk)
begin
q2 = a*b;
end
endmodule

This compiles withous warnings, but the result still isn't routed to
the "chip's" pads.

Gruss

Jan Bruns
 
"Jan Bruns" <post@abnuto.de> wrote in message news:ck7e8e$9u7$1@online.de...
[snip]
I've modified my testmul-example to:

module testmul(q, a,b, clk);
output [31:0] q;
reg [31:0] q2;
input [15:0] a,b;
input clk;
assign q = q2;
always @(posedge clk)
begin
q2 = a*b;
end
endmodule

This compiles withous warnings, but the result still isn't routed to
the "chip's" pads.
[snip]
Click to expand...

If the testmul is the only module in your design, the q output should make
it to the chip's pins. Look at any messages particularly in the map report
when you try to run the design through mapping and place&route.
 
The always block doesn't allow the "assign" keyword. It's for use outside
the always blocks. Your "pssibly working example" shouldn't compile if the
assign is in the always block.

"Jan Bruns" <post@abnuto.de> wrote in message news:ck76iu$td$1@online.de...
Hallo,

First, a working example:

module testrom1 (a,o);
input a;
output o;
reg o;
always @(a) begin
o = a;
end
endmodule

While the following 2 prodcuce errors:

module testrom2 (a,o);
input a;
output o;
reg o;
always @(a) assign o = a;
endmodule
-> ERROR:Xst:855 - Unsupported procedural assignment for signal <o>.

module testrom3 (a,o);
input a;
output o;
always @(a) assign o = a;
endmodule
ERROR:HDLCompilers:42 - testrom.v line 4 Illegal LHS of procedural
continuous assignment


Te me, this looked like xst doesn't like assignment to nets.

But, in contrast, look at this possibly working example:

module testmul(q, a,b, clk);
output [31:0] q;
reg [31:0] q;
input [15:0] a,b;
input clk;
always @(posedge clk)
begin
q = a*b;
assign q = q; //coment this, and the pad won't get result
end
endmodule

With "assign q = q;" commented out, timingan can't detect"a<0>(Pad) to
q<31>(Pad)"-Path.
What's the reason for this?

Gruss

Jan Bruns
Click to expand...
 
"Jan Bruns" <post@abnuto.de> wrote in message news:<ck7e8e$9u7$1@online.de>...
"John_H":
The always block doesn't allow the "assign" keyword. It's for use outside
the always blocks. Your "pssibly working example" shouldn't compile if the
assign is in the always block.

Hm, xst seems at least to allow assign outside of always-blocks.

On the other hand, the XST User Guide states:

| The assign / deassign statement must be performed in the
| same always block through an if /else statement.

and all of the 4 assign examples (3 of them are declared as non-workung
don't do this examples) in that book use assign within always-blocks.
Click to expand...
There are two types of 'assign' (as statements that use
'assign' as a keyword) in Verilog.

First one is called 'continuous assignment' and it must
occur outside any other initial and always block. This
type of statements are synthesizable.

assign a = b & c;

The second type is called 'procedural continuous assignment'
and occurs within a procedural block (that is initial or
always). It looks identical to the previous 'continuous
assignment', comes with its colonial cousin 'deassign'
statement and is not generally synthesizable. My suggestion
would be unless you are sure what you are doing, do not
use this contruct at all. You can still design and verify
all the logic of this world without them.

- Swapnajit.
--
SystemVerilog DPI tutorial on Project VeriPage:
http://www.project-veripage.com/dpi_tutorial_1.php
For subscribing to Project VeriPage mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>
 
"John_H" <johnhandwork@mail.com> wrote in message news:<WgG9d.34$Be6.2970@news-west.eli.net>...
The always block doesn't allow the "assign" keyword. It's for use outside
the always blocks. Your "pssibly working example" shouldn't compile if the
assign is in the always block.
Click to expand...
The "assign" keyword actually is allowed inside an always block; it just
isn't a continuous assignment. It means a different construct, called a
"procedural continuous assignment" or "quasi-continuous assignment". It
is used with a variable on the left-hand side, and creates a subprocess
that continuously assigns the value of the right-hand side expression to
the left-hand side. It overrides the effect of any normal procedural
assignments to the variable, and remains until removed with a "deassign"
statement.

It is probably not accepted by most synthesis tools, and is rarely used.
 
"Jan Bruns" <post@abnuto.de> wrote in message news:<ck76iu$td$1@online.de>...
Hallo,

First, a working example:

module testrom1 (a,o);
input a;
output o;
reg o;
always @(a) begin
o = a;
end
endmodule

While the following 2 prodcuce errors:

module testrom2 (a,o);
input a;
output o;
reg o;
always @(a) assign o = a;
endmodule
-> ERROR:Xst:855 - Unsupported procedural assignment for signal <o>.

module testrom3 (a,o);
input a;
output o;
always @(a) assign o = a;
endmodule
ERROR:HDLCompilers:42 - testrom.v line 4 Illegal LHS of procedural continuous assignment


Te me, this looked like xst doesn't like assignment to nets.
Click to expand...
It's not an assignment to a net! o is declared as a reg. Also, you
DO NOT put assign statements inside always blocks.

But, in contrast, look at this possibly working example:

module testmul(q, a,b, clk);
output [31:0] q;
reg [31:0] q;
input [15:0] a,b;
input clk;
always @(posedge clk)
begin
q = a*b;
assign q = q; //coment this, and the pad won't get result
end
endmodule
Click to expand...
The assign statement is completely illegal and the tools properly
complain.

With "assign q = q;" commented out, timingan can't detect"a<0>(Pad) to q<31>(Pad)"-Path.
Click to expand...
That's odd, but it seems to me that your code isn't working in the
first place, so the timing analysis will be bogus.

-a
 
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