Xor Code

[prasunp]

Hello:

Why won't this work? I am trying to find out if A = 0;

thanks


module Code(A,C);
input [31:0]A;
output C;

assign C = A~^0;


endmodule

 

[prasunp]

I guess I can also do this

assign DP_Out_Done = ( DP_Count_Zero == {D_Width{1'b0}} ) ? 1'b1 :
1'b0;

But how does this get synthesized? A mux?

Thanks

 

[michaelst@gmail.com]

Try this one:
assign A_eq_0 = ~(|A);

 

[Jason Zheng]

Actually, all synthesizers can do their best job if you take the
advantage of the verilog language and let them figure out the best way
to do it:

assign out = (a[31:0] == 32'b0);

By default, the synthesizer will find a logic design that fits that
description. It may not be the ideal tree structure that you hope for,
but once you put in a tight timing constraint, it will get close to it.

The reason why you shouldn't handcode the gates is:
1. You want portability, and a handcoded logic design is likely to take
advantage of the architecture features that's not available in other
architectures. It's ok if the synthesizers do this, but not you as a
designer.

2. It's tricky to do. Unless you use some synthesis directives, simply
by saying:
assign out = ~|a[31:0];
doesn't guarantee that you will get OR gates out the the synthesis. In
some architectures it might be more desirable to implement it in muxes.
Heck, it might be easier to implement it in RAM sometimes! Let the
synthesis tool decide this. Your job is just to let the synthesis tool
know what you want without ambiguity!

~jz

prasunp wrote:

I guess I can also do this

assign DP_Out_Done = ( DP_Count_Zero == {D_Width{1'b0}} ) ? 1'b1 :
1'b0;

But how does this get synthesized? A mux?

Thanks

 

[prasunp]

Thank you guys
Suggestions have been very useful.

Prasun

 

[General Schvantzkoph]

On Thu, 23 Feb 2006 23:35:19 -0800, prasunp wrote:

Hello:

Why won't this work? I am trying to find out if A = 0;

thanks


module Code(A,C);
input [31:0]A;
output C;

assign C = A~^0;


endmodule

assign C = A ==0;