Xilinx's version of Quartus' Signaltap?

[laserbeak43]

Hello,
I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Could someone please enlighten me?
Thanks,
Malik

 

[Alan Fitch]

laserbeak43 wrote:

Hello,
I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Could someone please enlighten me?
Thanks,
Malik

There's a feature comparison of different editions of Xilinx here:

http://www.xilinx.com/publications/matrix/Software_matrix.pdf

I believe the equivalent Xilinx feature is ChipScope,

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com

 

[Martin Thompson]

laserbeak43 <laserbeak43@gmail.com> writes:

Hello,
I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison. I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

 

[Andy Peters]

On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

Use the ChipScope Core Inserter. All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.
From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

-a

 

[Martin Thompson]

Andy Peters <google@latke.net> writes:

On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

10.1.3

Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds... Then click "write
CDC" button, import the result into the analyser. Still tedious

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html