Xilinx XST 9.1, Verilog 2-D arrays, always @*

U

Ulsk

Guest
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end
 
On 3ÔÂ17ČŐ, ĎÂÎç2Ęą28ˇÖ, "Ulsk" <a...@ljs.com> wrote:
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end
Click to expand...

I think the code can not be synthesize correctly by any tool not only
ISE!
 
"Homuncilus" <Sha.Craig@gmail.com> wrote in message
news:1174121624.193180.150560@n59g2000hsh.googlegroups.com...
On 3??17¨¨?, ????2¨şĄŔ28Ą¤?, "Ulsk" <a...@ljs.com> wrote:
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a
suboptimal
imbalanced adder-tree!
end

I think the code can not be synthesize correctly by any tool not only
ISE!
Click to expand...

ASIC synthesis tools (like Synopsys Design Compiler, Cadence RTL
Compiler, etc.) have no difficulty synthesizing the above example.
 
On 3月18日, 上午6时17分, "Ulsk" <a...@ljs.com> wrote:
"Homuncilus" <Sha.Cr...@gmail.com> wrote in message
news:1174121624.193180.150560@n59g2000hsh.googlegroups.com...
On 3??17¨¨?, ????2¨º¡À28¡¤?, "Ulsk" <a...@ljs.com> wrote:
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg  signed [15:0] table [0:255];
reg  signed [23:0] sum;

integer i;
always @*
begin
  sum = 0;
  for ( i =0; i < 256; i = i + 1 )
    sum = sum + table;  // yes, I know this will synthesize a
suboptimal
imbalanced adder-tree!
end

I think the code can not be synthesize correctly by any tool not only
ISE!

ASIC synthesis tools (like Synopsys Design Compiler, Cadence RTL
Compiler, etc.) have no difficulty synthesizing the above example.- 隐藏被引用文字 -

- 显示引用的文字 -
Click to expand...

Could you tell me the result about the above example being synthesized
by the ASIC tools and could you sure that the function runs well?
 
On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end
Click to expand...

Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilog simulator warns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements. ISE seems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John
 
On Mar 19, 11:00 am, "John McGrath" <tail...@gmail.com> wrote:
On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end

Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilog simulator warns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements. ISE seems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John
Click to expand...

I think the wrong isn't due to the sensitivity list. Do you sure the
error in ISE is caused by that?
 
On Mar 19, 5:59 am, "Homuncilus" <Sha.Cr...@gmail.com> wrote:
On Mar 19, 11:00 am, "John McGrath" <tail...@gmail.com> wrote:



On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end

Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilog simulator warns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements. ISE seems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John

I think the wrong isn't due to the sensitivity list. Do you sure the
error in ISE is caused by that?
Click to expand...

I ran the following testcase through ncverilog:

module test;

reg [7:0] array [0:7];
reg [2:0] idx;
reg [7:0] out;

always@*
begin
out = array[idx];
end

endmodule


The logfile gives the following warnings:

always@*
|
ncvlog: *W,STARMR (array.v,8|6): @* containing memory reference not
standard or portable.
out = array[idx];
ncvlog: *W,MRSTAR (array.v,10|11): memory reference that was not
standard in @*.
module worklib.test:v

So clearly always @* when used with an array is non part of the
verilog standard.

Cheers
John
 
On Mar 19, 7:31 am, "John McGrath" <tail...@gmail.com> wrote:
On Mar 19, 5:59 am, "Homuncilus" <Sha.Cr...@gmail.com> wrote:



On Mar 19, 11:00 am, "John McGrath" <tail...@gmail.com> wrote:

On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end

Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilog simulator warns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements. ISE seems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John

I think the wrong isn't due to the sensitivity list. Do you sure the
error in ISE is caused by that?

I ran the following testcase through ncverilog:

module test;

reg [7:0] array [0:7];
reg [2:0] idx;
reg [7:0] out;

always@*
begin
out = array[idx];
end

endmodule

The logfile gives the following warnings:

always@*
|
ncvlog: *W,STARMR (array.v,8|6): @* containing memory reference not
standard or portable.
out = array[idx];
ncvlog: *W,MRSTAR (array.v,10|11): memory reference that was not
standard in @*.
module worklib.test:v

So clearly always @* when used with an array is non part of the
verilog standard.

Cheers
John
Click to expand...


You could alternately use:

always @(idx) in place of always@*
 
On Mar 19, 7:35 am, "bluesclues" <deepak.l...@gmail.com> wrote:
On Mar 19, 7:31 am, "John McGrath" <tail...@gmail.com> wrote:



On Mar 19, 5:59 am, "Homuncilus" <Sha.Cr...@gmail.com> wrote:

On Mar 19, 11:00 am, "John McGrath" <tail...@gmail.com> wrote:

On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end

Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilog simulator warns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements. ISE seems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John

I think the wrong isn't due to the sensitivity list. Do you sure the
error in ISE is caused by that?

I ran the following testcase through ncverilog:

module test;

reg [7:0] array [0:7];
reg [2:0] idx;
reg [7:0] out;

always@*
begin
out = array[idx];
end

endmodule

The logfile gives the following warnings:

always@*
|
ncvlog: *W,STARMR (array.v,8|6): @* containing memory reference not
standard or portable.
out = array[idx];
ncvlog: *W,MRSTAR (array.v,10|11): memory reference that was not
standard in @*.
module worklib.test:v

So clearly always @* when used with an array is non part of the
verilog standard.

Cheers
John

You could alternately use:

always @(idx) in place of always@*
Click to expand...

Maybe, but it would not work if the contents of the array were updated
by a different process, independent of idx.
I'm not sure how this would be syntesized - It may infer latches on
the output, or error out. I'd be interested to see what happens

Personally, for this example (asynch read of array elements) I'd use a
continuous assignment.

But personally I think verilog language should support @* in an array
context, it works in all other contexts, and prevents unintentional
latch inferral.
As we can see from Duth, this will be added to ISE soon, and some
other tools support it too, but they just warn that it is not strictly
part of the standard.

Cheers
John
 
On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end
Click to expand...

Ulsk,

I've heard that this is a "grey" area of the Verilog standard. It
shouldn't be at
all - the intended behavior is quite clear in your example, and the
tools should do the correct thing. Unfortunetly XST doesn't get it
right yet.
Xilinx promised to fix this is ISE9.x. Now, they've put it off again
until 10.x.

We've used VERY similar constructs - except we used SystemVerilog
packed arrays, instead of your
verilog-2001 "unpacked" array equivalent. This has worked fine for us
in ASIC and FPGA flows.
It works with VCS, modelsim, dc_shell, and Precision. Of course,
you'll need to use the
"Systemverilog" switch of the tools - which Xilinx doesn't have yet
either.

For your example in SystemVerilog, just change the table definition
to:
reg signed [ 255 : 0 ] [ 15 : 0 ] table;

And it would work. I'm thinking in the IEEE Std 1800-2005
(SystemVerilog IEEE standard),
they may have cleaned this up, and you're original example would work.

--Mark
 
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