Xilinx XST 6.x and Verilog-2001?

[Allan Herriman]

Hi,

Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001?

This document
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html
shows that the older version, XST 5.x, has partial support for Verilog
2001.

I was wondering if the support is better in the newer version of ISE.

In particular, I'm interested in knowing if 'generate' works, and
whether arrays of instances work. The latter was actually added to
the language in 1995, but XST 5.x doesn't seem to support it.

Regards,
Allan.

 

[Steve Lass]

Allan Herriman wrote:

Hi,

Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001?

This document
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html
shows that the older version, XST 5.x, has partial support for Verilog
2001.

I was wondering if the support is better in the newer version of ISE.

Yes. You can see the main improvements at:

http://toolbox.xilinx.com/docsan/xilinx6/swcol/whatsnew.htm

In particular, I'm interested in knowing if 'generate' works, and
whether arrays of instances work.

XST supports both of these in version 6.1i.

Steve

The latter was actually added to
the language in 1995, but XST 5.x doesn't seem to support it.

Regards,
Allan.