M
Mukesh Chugh
Guest
Hi,
I am facing following issues when using Xpower to calculate the
dynamic power for my design:
Tools being used:
Xilinx ISE 6.2, Xpower 6.2.03i
ModelSim XE II/ Starter 5.7g
I am generating the .vcd file during post PAR simulation and then
using this file for xpower along with .ncd and .pcf files. I get a lot
of warnings like:
WARNINGower:763 - Only 41% of the design signals toggle.
WARNINGower:216 - VCDFile(564214): $dumpoff command encountered, all
simulation data after this will be ignored.
INFOower:555 - Estimate is reasonable based on analysis of the
design, user
WARNINGower:91 - Can't change frequency of net clk to 166.67Mhz.
WARNINGower:91 - Can't change frequency of net clk to 165.83Mhz.
WARNINGower:91 - Can't change frequency of net clk_BUFGP/IBUFG to
165.83Mhz.
WARNINGower:91 - Can't change frequency of net clk_BUFGP to
165.83Mhz.
WARNINGower:91 - Can't change frequency of net GLOBAL_LOGIC0 to
0.83Mhz.
WARNINGower:91 - Can't change frequency of net ce_IBUF to 0.83Mhz.
WARNINGower:91 - Can't change frequency of net clk to 165.83Mhz.
WARNINGower:91 - Can't change frequency of net clk_BUFGP/IBUFG to
165.83Mhz.
parsing completed in: 0 secs
WARNINGower:91 - Can't change frequency of net ce_IBUF to 0.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in4_0_IBUF to
0.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in4_1_IBUF to
0.83Mhz.
.......
WARNINGower:91 - Can't change frequency of net gateway_in4_8_IBUF to
0.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in8_IBUF to
25.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in10_IBUF to
26.67Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in9_IBUF to
25.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in5_0_IBUF to
1.67Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in5_1_IBUF to
0.83Mhz.
.......
..
WARNINGower:91 - Can't change frequency of net gateway_in3_3_IBUF to
26.67Mhz.
WARNINGower:763 - Only 42% of the design signals toggle.
WARNINGower:763 - Only 42% of the design signals toggle.
the report summary is
Power summary: I(mA) P(mW)
----------------------------------------------------------------
Total estimated power consumption: 553
---
Vccint 1.50V: 146 220
Vccaux 3.30V: 100 330
Vcco33 3.30V: 1 3
---
Clocks: 0 0
Inputs: 3 5
Logic: 61 91
Outputs:
Vcco33 0 0
Signals: 17 26
---
Quiescent Vccint 1.50V: 65 98
Quiescent Vccaux 3.30V: 100 330
Quiescent Vcco33 3.30V: 1 3
Startup Vccint 1.5V: 200
Startup Vccaux 3.3V: 100
Startup Vcco33 3.3V: 50
---
My Questions:
- How come I get clock power zero? In another smaller testdesign of
counters, I do get some power although logic power in that case is
very less.
- The activity rate for clock nets is zero. How?
- I get the correct simulation but the power results seem incorrect.
- Whats the meaningof such warnings?
--
Mukesh
I am facing following issues when using Xpower to calculate the
dynamic power for my design:
Tools being used:
Xilinx ISE 6.2, Xpower 6.2.03i
ModelSim XE II/ Starter 5.7g
I am generating the .vcd file during post PAR simulation and then
using this file for xpower along with .ncd and .pcf files. I get a lot
of warnings like:
WARNINGower:763 - Only 41% of the design signals toggle.
WARNINGower:216 - VCDFile(564214): $dumpoff command encountered, all
simulation data after this will be ignored.
INFOower:555 - Estimate is reasonable based on analysis of the
design, user
WARNINGower:91 - Can't change frequency of net clk to 166.67Mhz.
WARNINGower:91 - Can't change frequency of net clk to 165.83Mhz.
WARNINGower:91 - Can't change frequency of net clk_BUFGP/IBUFG to
165.83Mhz.
WARNINGower:91 - Can't change frequency of net clk_BUFGP to
165.83Mhz.
WARNINGower:91 - Can't change frequency of net GLOBAL_LOGIC0 to
0.83Mhz.
WARNINGower:91 - Can't change frequency of net ce_IBUF to 0.83Mhz.
WARNINGower:91 - Can't change frequency of net clk to 165.83Mhz.
WARNINGower:91 - Can't change frequency of net clk_BUFGP/IBUFG to
165.83Mhz.
parsing completed in: 0 secs
WARNINGower:91 - Can't change frequency of net ce_IBUF to 0.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in4_0_IBUF to
0.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in4_1_IBUF to
0.83Mhz.
.......
WARNINGower:91 - Can't change frequency of net gateway_in4_8_IBUF to
0.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in8_IBUF to
25.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in10_IBUF to
26.67Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in9_IBUF to
25.83Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in5_0_IBUF to
1.67Mhz.
WARNINGower:91 - Can't change frequency of net gateway_in5_1_IBUF to
0.83Mhz.
.......
..
WARNINGower:91 - Can't change frequency of net gateway_in3_3_IBUF to
26.67Mhz.
WARNINGower:763 - Only 42% of the design signals toggle.
WARNINGower:763 - Only 42% of the design signals toggle.
the report summary is
Power summary: I(mA) P(mW)
----------------------------------------------------------------
Total estimated power consumption: 553
---
Vccint 1.50V: 146 220
Vccaux 3.30V: 100 330
Vcco33 3.30V: 1 3
---
Clocks: 0 0
Inputs: 3 5
Logic: 61 91
Outputs:
Vcco33 0 0
Signals: 17 26
---
Quiescent Vccint 1.50V: 65 98
Quiescent Vccaux 3.30V: 100 330
Quiescent Vcco33 3.30V: 1 3
Startup Vccint 1.5V: 200
Startup Vccaux 3.3V: 100
Startup Vcco33 3.3V: 50
---
My Questions:
- How come I get clock power zero? In another smaller testdesign of
counters, I do get some power although logic power in that case is
very less.
- The activity rate for clock nets is zero. How?
- I get the correct simulation but the power results seem incorrect.
- Whats the meaningof such warnings?
--
Mukesh