Xilinx Webpack

[mep]

Hi there
I teach classes in VHDL and uses Xilinx Webpack as a tool for this.
Unfortunately, the new module wizard always set type std_logic for
I/O-lines. This makes it very hard to learn the students about the other
types.
Does anybody know if this can be changed - and how?
Mogens

 

[Mike Treseler]

mep wrote:

Hi there
I teach classes in VHDL and uses Xilinx Webpack as a tool for this.
Unfortunately, the new module wizard always set type std_logic for
I/O-lines. This makes it very hard to learn the students about the other
types.

Consider using the Modelsim program included
with webpack to teach VHDL language.

-- Mike Treseler

 

[mep]

Hi Mike
Not really, because in all the drills, the students end up programming a
CPLD or a FPGA from Xilinx. In this way they can themselves check the
solutions.
But maybe I should take a closer look, because there are a number of
problems with webpack.
Mogens

"Mike Treseler" <mike_treseler@comcast.net> skrev i en meddelelse
news:rKudnSkpz5d-1srcRVn-sg@comcast.com...

mep wrote:
Hi there
I teach classes in VHDL and uses Xilinx Webpack as a tool for this.
Unfortunately, the new module wizard always set type std_logic for
I/O-lines. This makes it very hard to learn the students about the other
types.

Consider using the Modelsim program included
with webpack to teach VHDL language.

-- Mike Treseler

 

[Alex Gibson]

"mep" <mpe@metanic.dk> wrote in message
news:4157bc0a$0$253$edfadb0f@dread14.news.tele.dk...

Hi Mike
Not really, because in all the drills, the students end up programming a
CPLD or a FPGA from Xilinx. In this way they can themselves check the
solutions.
But maybe I should take a closer look, because there are a number of
problems with webpack.
Mogens

Easy to copy the code from in modelsimand paste it back into project
navigator.
Or use the add a copy of the source feature in
the module wizard and in project navigator.

We use the full version of ise in the lab
(via university program http://university.xilinx.com/ )
and students have webpack to use at home.

If you have problems with webpack go here
http://xup.msu.edu/support/index.htm

Surely it is up to the instructor to
teach them about all the types in vhdl not the module wizard ?

Could always set a few small assignments where they have to use
some of the other types or give them a limit on the number
of std_logic I/Os they can use.


Alex

 

[Laurent Gauch]

skip any wizard !
Your students need to learn the basic of VHDL and NOT the software troubles.

You can provide some VHDL generic code of DFF, shift register, counter ...

For a nice VHDL memo goto http://www.amontec.com/fix/vhdl_memo/index.html

Larry


Mike Treseler wrote:

mep wrote:

Hi there
I teach classes in VHDL and uses Xilinx Webpack as a tool for this.
Unfortunately, the new module wizard always set type std_logic for
I/O-lines. This makes it very hard to learn the students about the other
types.


Consider using the Modelsim program included
with webpack to teach VHDL language.

-- Mike Treseler

 

[rickman]

Laurent Gauch wrote:

skip any wizard !
Your students need to learn the basic of VHDL and NOT the software troubles.

You can provide some VHDL generic code of DFF, shift register, counter ...

For a nice VHDL memo goto http://www.amontec.com/fix/vhdl_memo/index.html

I don't see a default type in a wizard as "troubles". Sure the GUI
stuff will have more bugs than simpler software, but the GUI is what
most people use and it is not unreasonable to use it in a classroom. I
especially like the idea of not making students spend time typing in
lists of signals several times for module definitions. I prefer that
they learn the basics of how to use an HDL and how to code. I almost
never start from scratch in my VHDL. I copy from an old module and just
change the names. I even have defined editor macros to allow me to type
in the signal names once and do a search and replace to change the list
to the other formats, component declarations and instantiations.

Why make the students do a lot of work they won't be doing in the real
world? I hated that sort of make-work when I was in school.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
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