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Urban Stadler

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hi

i have the following problem:
i have written some code and part of it is:

RAM_CONTROL_COMB: process(Sensor_Data_Ready, RAM_BHE, RAM_BLE, Sensor_Data)
begin

RAM_Data <= "ZZZZZZZZZZZZZZZZ";
s_RAM_Address_Count_Sensor <= '0';

if Sensor_Data_Ready'event and Sensor_Data_Ready = '1' then
if RAM_BHE = '0' then
RAM_Data(15 downto 8) <= Sensor_Data;
elsif RAM_BLE = '0' then
RAM_Data(7 downto 0) <= Sensor_Data;
end if;
end if;

if RAM_BLE'event and RAM_BLE = '1' then
s_RAM_Address_Count_Sensor <= '1';
end if;
end process RAM_CONTROL_COMB;

i get the following error message:

RROR:Xst:827 - D:/CodeGeeks/Elektronik/VHDL/FingerTip/FgTp.vhdl line
191: Signal RAM_Data<7> cannot be synthesized, bad synchronous
description.

line 191 is the declaration of the process. the simulation works. i can get
rid of the error if i put the two lines
RAM_Data <= "ZZZZZZZZZZZZZZZZ";
s_RAM_Address_Count_Sensor <= '0';
at the verry end of the process.
why does this make a difference. after that the simulation doesnt work
anymore.

thanks for any help
urban
 
well i have a ram module that has 2 different write enable ports. one for
the high byte an one for the low byte.



"Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag
news:cfv04u$70v$04$1@news.t-online.com...
"Urban Stadler" <u.stadler@pfeilheim.sth.ac.at> wrote in message
news:dMCUc.112408$sh.96444@fed1read06...
hi

i have the following problem:
i have written some code and part of it is:

RAM_CONTROL_COMB: process(Sensor_Data_Ready, RAM_BHE, RAM_BLE,
Sensor_Data)
begin

RAM_Data <= "ZZZZZZZZZZZZZZZZ";
s_RAM_Address_Count_Sensor <= '0';

if Sensor_Data_Ready'event and Sensor_Data_Ready = '1' then
if RAM_BHE = '0' then
RAM_Data(15 downto 8) <= Sensor_Data;
elsif RAM_BLE = '0' then
RAM_Data(7 downto 0) <= Sensor_Data;
end if;
end if;

the above assumes you have RAM module from 2 block rams, each 8 bit wide
and
with separate wr enable ports. I would say the code as is would not
synthesise in most cases.

rethink your logic!

antti
xilinx.openchip.org
Click to expand...
 
"Urban Stadler" <u.stadler@pfeilheim.sth.ac.at> wrote in message
news:dMCUc.112408$sh.96444@fed1read06...
hi

i have the following problem:
i have written some code and part of it is:

RAM_CONTROL_COMB: process(Sensor_Data_Ready, RAM_BHE, RAM_BLE,
Sensor_Data)
begin

RAM_Data <= "ZZZZZZZZZZZZZZZZ";
s_RAM_Address_Count_Sensor <= '0';

if Sensor_Data_Ready'event and Sensor_Data_Ready = '1' then
if RAM_BHE = '0' then
RAM_Data(15 downto 8) <= Sensor_Data;
elsif RAM_BLE = '0' then
RAM_Data(7 downto 0) <= Sensor_Data;
end if;
end if;
Click to expand...
the above assumes you have RAM module from 2 block rams, each 8 bit wide and
with separate wr enable ports. I would say the code as is would not
synthesise in most cases.

rethink your logic!

antti
xilinx.openchip.org
 
Urban Stadler wrote:


RAM_CONTROL_COMB: process(Sensor_Data_Ready, RAM_BHE, RAM_BLE, Sensor_Data)
begin

RAM_Data <= "ZZZZZZZZZZZZZZZZ";
s_RAM_Address_Count_Sensor <= '0';

if Sensor_Data_Ready'event and Sensor_Data_Ready = '1' then
if RAM_BHE = '0' then
RAM_Data(15 downto 8) <= Sensor_Data;
elsif RAM_BLE = '0' then
RAM_Data(7 downto 0) <= Sensor_Data;
end if;
end if;

if RAM_BLE'event and RAM_BLE = '1' then
s_RAM_Address_Count_Sensor <= '1';
end if;
end process RAM_CONTROL_COMB;

i get the following error message:

RROR:Xst:827 - D:/CodeGeeks/Elektronik/VHDL/FingerTip/FgTp.vhdl line
191: Signal RAM_Data<7> cannot be synthesized, bad synchronous
description.
Click to expand...
Think like the simulator: Everytime Sensor_Data_Ready, RAM_BHE, RAM_BLE
or Sensor_Data changes, this process is triggered and then

RAM_Data <= "ZZZZZZZZZZZZZZZZ";
s_RAM_Address_Count_Sensor <= '0';

are set. (And only during a rising_edge of Sensor_Data_Ready something
different is assigned.)
What do you think this could be in Hardware? I have no idea and your
synthesis tool, too.

Use a synchronous FF with async reset:

process(asyc_reset,clock)
begin
if (asyc_reset='1') then
-- do some reset
elsif rising_edge(clock) then
-- do what you want
end if;
end process;


Furthermore you use _two_ "edge detectors" within one process, which
leads to the synthesis tool error. Only a few synthesis tools support
dual-edge-fliflops, so in most cases this is forbidden.
But your problem is very easy to solve, because in the 1st
edge-triggered block RAM_Data is written to and in the 2nd
s_RAM_Address_Count_Sensor is written to. -> Just split this process
into two processes. The synthesis tool is not smart enough to detect,
that in you case this is not a dual-edge-FF. It does simply synthax
checking.

Ralf
 
On Tue, 17 Aug 2004 23:34:37 +0200, "Urban Stadler"
<u.stadler@pfeilheim.sth.ac.at> wrote:

hi

i have the following problem:
i have written some code and part of it is:

RAM_CONTROL_COMB: process(Sensor_Data_Ready, RAM_BHE, RAM_BLE, Sensor_Data)

if Sensor_Data_Ready'event and Sensor_Data_Ready = '1' then

if RAM_BLE'event and RAM_BLE = '1' then
Click to expand...
This process appears to have two clock signals.

i get the following error message:
RROR:Xst:827 - D:/CodeGeeks/Elektronik/VHDL/FingerTip/FgTp.vhdl line
191: Signal RAM_Data<7> cannot be synthesized, bad synchronous
description.
Click to expand...
It is likely that the synthesis tool cannot accept such a process, even
if it simulates the way you want.
Try two separate processes, with one clock each.

- Brian
 
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