Xilinx WebPack Spartan3 DCM implementation problem

[Nicolas Matringe]

Hello
I am trying to implement a PCI design in a Spartan3 device. Everything
went quite well until I decided to use a DCM to remove the last timing
problems I got.
Since I put the DCM in my design, ISE refuses to P&R.
Here is what I got in the P&R report file:

WARNING:Ncd:218 - The component "pci_clk_in" specified in the .PCF file
was not
found in the design. Please verify that:
1. the specified component actually exists in the original design,
2. the trimming report in the .MRP file does not report it as having
been
trimmed, and also
3. the specified component record in the .PCF file is spelled correctly.
WARNING:Ncd:216 - Ignoring constraint <COMP "pci_clk_in" LOCATE = SITE "D9"
LEVEL 1; > because comp, pci_clk_in, not found

and so on...
It looks like my clock was removed somewhere.
I entered the constraints using the constraints editor so I'm sure I
din't misspell the signal names...
I'm lost.
Any help welcome.

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Antti Lukats]

"Nicolas Matringe" <nicolasmatringe001@numeri-cable.fr> wrote in message
news:412219B6.2070303@numeri-cable.fr...

Hello
I am trying to implement a PCI design in a Spartan3 device. Everything
went quite well until I decided to use a DCM to remove the last timing
problems I got.

what PCI core are you using and why did you want to use DCM?
DCMs are not normally used in the PCI cores.
So may advice is: remove the DCM and get the core implemented in way that it
passes timing.

Since I put the DCM in my design, ISE refuses to P&R.
Here is what I got in the P&R report file:

WARNING:Ncd:218 - The component "pci_clk_in" specified in the .PCF file

the safest way always is to use one .UCF and text editor for the
constraints
..NCF and .PCF files sound like trouble... at least the .NCF does sometimes
make problem (with ChipScopePro)

recheck your design and reports again to see that the nets by that exact
name exist and have not been renamed and nothing isnt trimmed etc..

antti
http://www.openchip.org/ebay/FreePCI_Cores_Report.html

 

[Nicolas Matringe]

what PCI core are you using and why did you want to use DCM?

It's a VHDL core, not one of X's cores.
I wanted to use the DCM to remove clock delays that caused the design
not to meet some timing constraints.

DCMs are not normally used in the PCI cores.

I suppose it depends on the cores...

So may advice is: remove the DCM and get the core implemented in way that it
passes timing.

My problem is that it doesn't pass.

the safest way always is to use one .UCF and text editor for the
constraints

That's what I usely do. The only risk is to misspell some signal name.

.NCF and .PCF files sound like trouble... at least the .NCF does sometimes
make problem (with ChipScopePro)

I didn't touch these, they are automatically generated (and that's why I
am really puzzled)

recheck your design and reports again to see that the nets by that exact
name exist and have not been renamed and nothing isnt trimmed etc..

Why do you think I used the constraints editor and not a simple text
editor? )

I finally removed all the ISE-generated files (I only kept the VHDL, UCF
and the NPL files) and reran the whole process and it worked fine.

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/